Shared CRC-DBI Bus Encoding for Lower Pin Count Memory I/O
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Solution Overview
Problem
Conventional memory interface protocols require separate physical pins for CRC and DBI, increasing pin count and limiting data transfer capacity despite efforts to reduce form factor and power consumption.
Innovation Solution
A combined CRC and DBI encoding scheme that compresses CRC and DBI information onto a single set of pins, allowing additional data bits to be embedded in the CRC, without separate pins for DBI, while maintaining error detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate physical pins are used for CRC and DBI transmission, then error detection and power reduction functions are reliably implemented, but pin count increases and data transfer capacity is limited
Solution Approach 1:
The patent combines CRC and DBI functions into a single pin by merging their information streams. The receiver sweeps through multiple candidate DBI vectors and uses CRC verification to identify the correct original data, allowing both error detection and power reduction to share the same physical interface without dedicated separate pins
Solution Approach 2:
The single pin serves multiple functions: it transmits both CRC information for error detection and DBI information for power reduction, while also carrying additional data bits. This multi-functional approach eliminates the need for separate dedicated pins for each function
2Device complexity
If data bus bitlength is fixed by pin count, then I/O pin count is reduced, but data transfer capacity is limited
Solution Approach 1:
The patent adds an additional dimension to data transmission by embedding extra data bits within the CRC field. Instead of expanding the data bus width, the invention utilizes the CRC bits to carry additional information, effectively increasing data transfer capacity without adding physical pins
3Productivity
If CRC bits are used for additional data transfer, then data transfer capacity increases, but error detection accuracy may be compromised
Solution Approach 1:
The patent applies partial action by using only a portion of the CRC bits for additional data embedding while maintaining sufficient CRC bits for error detection. The receiver sweeps through candidate DBI vectors and verifies using CRC, ensuring that error detection accuracy is maintained even with embedded data bits
Data Source
AI summary
Disclosed herein is transmission and reception scheme for communicating data over a data bus and determining errors in the communicated data. The system includes a transmitter circuitry and a receiver circuitry. The transmitter circuitry generates a CRC code based on an input data word, encodes the input data word with a data-bus inversion (DBI) vector, and transmits the DBI-encoded data word along with the CRC code to the receiver circuitry. The receiver circuitry decodes, over a plurality of candidate DBI vectors, the DBI-encoded data word based on each candidate DBI vector, computes an associated CRC value for each candidate data word, and determines a reconstructed input data word based on which associated CRC value of the plurality of candidate data words matches the CRC code.