Shared-Matrix CRC Circuit for DRAM Error Detection

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

As DRAMs shrink in size, bit errors in memory cells increase, leading to decreased yield and operational efficiency, existing error detection methods in semiconductor memory devices are inadequate in effectively addressing these errors.

Innovation Solution

An error detection code generation circuit is introduced, comprising a first and second CRC engine and an output selection engine, which generates error detection code bits using a shared generation matrix, merging first and second unit data with DBI bits to detect errors in semiconductor memory devices, thereby enhancing error detection capabilities while reducing hardware overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM size is reduced to increase storage capacity, then storage density is improved, but bit error rate increases

Engineering Contradiction:

Improvestorage densityVSAvoidbit error rate

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The data is divided into multiple unit data groups, and separate CRC engines are allocated to different data bus widths (e.g., first CRC engine for 8-bit data, second CRC engine for 16-bit data). This segmentation allows tailored error detection for each data segment, improving overall reliability while maintaining high storage density through efficient use of memory resources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically changes operational parameters by selecting different code rate modes (first code rate or second code rate) based on data characteristics. The mode signal switches between different CRC engine configurations, adapting the error detection strength to match the data requirements, thereby maintaining high reliability across varying storage densities.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If multiple CRC engines with different generation matrices are used to improve error detection, then error detection capability is improved, but device complexity increases

Engineering Contradiction:

Improveerror detection capabilityVSAvoidhardware overhead

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Multiple CRC engines are designed to share a common generation matrix structure, allowing them to perform different error detection functions using the same hardware resources. The engines can be selectively activated based on data bus width and code rate mode, providing universal error detection capability across different data formats without requiring completely separate hardware for each case.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically selects which CRC engine to use based on the mode signal and data characteristics. The output selection engine chooses between first and second error detection code bits in real-time, allowing the system to adapt its error detection strength and hardware usage dynamically, thereby balancing reliability improvement with complexity management.

Inventive Principle:

Principle #15Dynamics

3Measurement precision

If separate error detection codes are generated for different data bus widths, then error detection precision is improved, but processing time increases

Engineering Contradiction:

Improveerror detection precisionVSAvoidprocessing time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

Error detection code generation is performed in parallel with data processing operations. The CRC engines generate error detection codes simultaneously as data is being transferred and processed, rather than as a separate sequential step. This preliminary action reduces the overall processing time while maintaining high error detection precision through dedicated engines for different data widths.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The error detection process continues continuously alongside data transmission and processing operations. Multiple CRC engines operate concurrently on different data streams, ensuring that error detection is an ongoing process rather than an intermittent check. This continuous operation maintains high detection precision while minimizing additional processing time through efficient resource utilization.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11438016B2Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

Publication Date: 2022.09.06 SAMSUNG ELECTRONICS CO LTD

AI summary

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.