Shared Crossbar Interface Pool for Bandwidth and Chip Area

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Solution Overview

Problem

Existing crossbar switches face challenges in achieving high data speed and bandwidth capacity while minimizing chip size, as they often require dedicated connectivity resources for each ingress node, leading to increased area penalties and congestion.

Innovation Solution

Implementing a shared hardware interface system where multiple ingress nodes share a pool of hardware interfaces, managed by a central logic circuit or mechanisms that prevent collisions and absorb bursts, allowing for efficient data routing without a central controller in some cases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated connectivity resources are allocated for each ingress node, then reliability of data transmission is improved, but chip area increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple ingress nodes share a common hardware interface pool through the crossbar circuit, consolidating what would otherwise be dedicated separate interfaces. This merging reduces the total number of hardware interfaces needed while maintaining reliable data transmission through the shared resource architecture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hardware interfaces in the pool serve multiple ingress nodes simultaneously, making each interface universal rather than dedicated to a single node. This multi-functionality allows the same hardware interface to be dynamically allocated to different ingress nodes based on traffic needs, reducing overall chip area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If more hardware interfaces are provided for each ingress node, then bandwidth capacity is improved, but device complexity increases

Engineering Contradiction:
Improvebandwidth capacityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The crossbar circuit merges multiple ingress nodes and a pool of hardware interfaces into a unified switching fabric, enabling high bandwidth capacity without requiring each ingress node to have dedicated complex interface circuits. The shared architecture reduces overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system dynamically allocates hardware interfaces from the pool to ingress nodes based on real-time traffic demands, rather than providing static dedicated interfaces. This dynamic allocation achieves high bandwidth capacity while keeping the hardware interface pool size manageable, reducing device complexity.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If the number of ingress nodes is increased, then adaptability is improved, but congestion and collisions increase

Engineering Contradiction:
Improvenetwork adaptabilityVSAvoidcongestion and collisions
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The crossbar circuit acts as an intermediary between ingress nodes and the hardware interface pool, managing traffic flow and preventing direct collisions. This intermediary control mechanism allows multiple ingress nodes to access the shared interfaces without excessive congestion or collisions, maintaining network adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250392555A1Shared hardware interface for optimizing crossbar
Publication Date: 2025.12.25 MELLANOX TECHNOLOGIES LTD(IL)
  • US20250392555A1 patent drawing
  • US20250392555A1 patent drawing
  • US20250392555A1 patent drawing

AI summary

An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress nodes and one or more egress nodes. The plurality ingress nodes share the shared hardware interface. The shared hardware interface includes a pool of hardware interfaces, and the plurality of ingress nodes share the pool of hardware interfaces.