Shared-Current Clock Driver Circuit for Low-Jitter Array Timing
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Solution Overview
Problem
Existing low power clocking solutions for large arrays consume excessive power due to the use of broadband drivers, leading to increased uncorrelated jitter and inferior dynamic range per milliwatt metric.
Innovation Solution
A clock driver circuit comprising a multiple phase divider and a buffer that share a common current from a supply rail, with the buffer providing impedance transformation to prevent kickback noise and reduce power consumption, allowing for efficient low power clock distribution with reduced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If broadband drivers are used to distribute clock signals to large arrays, then clock distribution coverage is improved, but power consumption increases significantly
Solution Approach 1:
The clock distribution system is segmented into multiple low-power clock drivers distributed across the array, each serving a local region. This replaces the conventional approach of using a few high-power broadband drivers to cover the entire array, thereby reducing overall power consumption while maintaining adequate clock distribution coverage.
Solution Approach 2:
The patent implements local clock buffering and distribution, where each array element or small group of elements has its own clock buffer. This local quality approach ensures that clock signals are regenerated and distributed locally, reducing the power consumption of long-distance clock distribution while maintaining signal integrity across the entire array.
2Length of stationary object
If broadband drivers are used for clock distribution, then clock signal reach is improved, but uncorrelated jitter increases
Solution Approach 1:
The patent uses preliminary clock buffering and signal conditioning at each array element before the clock signal is distributed further. This preliminary action cleans up the clock signal early in the distribution path, preventing the accumulation of jitter that would occur in long broadband distribution routes, thereby maintaining lower uncorrelated jitter across the entire array.
3Reliability
If additional clock receiver blocks are added to correct clock levels, then clock signal quality is improved, but dynamic range per milliwatt metric deteriorates
Solution Approach 1:
The patent merges the clock buffering, signal conditioning, and distribution functions into integrated low-power clock driver circuits located at each array element. This consolidation eliminates the need for separate additional clock receiver blocks, maintaining clock signal quality while reducing the overall component count and power consumption, thereby improving the dynamic range per milliwatt metric.
Data Source
AI summary
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.