Shared CXL Memory Buffering for SSD Map Data Management

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Solution Overview

Problem

The capacity limitations of buffer memories in storage devices restrict the ability to manage increasing map data sizes, especially in high-capacity SSDs, necessitating either design changes or additional integration of buffer memory, which affects performance.

Innovation Solution

A computing system architecture where a shared CXL memory is used as a buffer for multiple storage devices, allowing them to communicate through a homogeneous CXL interface, eliminating the need for separate buffer memories in each device and enabling efficient management of large map data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If each storage device has its own buffer memory for managing map data, then the storage device can independently manage its map data, but the buffer memory capacity is limited and cannot support high-capacity SSDs

Engineering Contradiction:
Improvemap data capacityVSAvoidbuffer memory capacity limitation
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Multiple storage devices share a common buffer memory through the CXL interface, consolidating what were previously separate buffer memory capacities into a single pooled resource. This allows the system to handle larger total map data capacities without requiring each individual storage device to have proportionally large buffer memories.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The common buffer memory serves multiple storage devices simultaneously, making it a universal resource that can be dynamically allocated and accessed by any connected storage device. This multi-functional approach allows the buffer to support high-capacity SSDs while maintaining performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If additional buffer memory is integrated into each storage device, then the buffer memory capacity increases, but the device complexity and cost increase

Engineering Contradiction:
Improvebuffer memory capacityVSAvoidstorage device structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Instead of adding more buffer memory to each storage device, the system merges the buffer memory function into a shared resource accessible by multiple devices. This reduces the complexity of individual storage devices while increasing the overall system capacity.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If a shared common buffer memory is used for multiple storage devices, then the buffer memory capacity is sufficient for high-capacity SSDs, but the interface complexity increases

Engineering Contradiction:
Improvebuffer memory capacityVSAvoidinterface structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The CXL interface acts as an intermediary layer that manages the shared buffer memory access between multiple storage devices and the host. This standardized interface handles the complexity of arbitration, memory mapping, and data transfer, shielding the individual devices from the complexity of shared resource management.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If traditional buffer memory architecture is used, then the device design is simple, but the performance is limited by buffer memory capacity

Engineering Contradiction:
Improvestorage performanceVSAvoidmemory management structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system dynamically allocates and manages buffer memory resources across multiple storage devices based on actual access patterns and capacity requirements. This dynamic approach allows the system to optimize performance by allocating buffer resources where they are most needed, rather than using a static fixed allocation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12481457B2Operating method of memory device for managing map data of each of plurality of storage devices, computing system including memory device, and operating method of computing system
Publication Date: 2025.11.25 SAMSUNG ELECTRONICS CO LTD
  • US12481457B2 patent drawing
  • US12481457B2 patent drawing
  • US12481457B2 patent drawing

AI summary

An operating method of a memory device which communicates with a first storage device and a second storage device through an interface circuit is provided. The method includes receiving, from a host device, a first request including a command and a first logical block address; obtaining, based on the first logical block address, a first physical block address with reference to first map data dedicated for the first storage device; and sending, to the first storage device through the interface circuit, a second request including the first physical block address and the command.