Shared-DAC Phase Interpolator With Bleeder Current Control
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Solution Overview
Problem
Current mode logic (CML) systems require separate dedicated digital-to-analog converters (DACs) for each channel, which is inefficient for handling multiple differential channels, leading to increased complexity and cost.
Innovation Solution
A phase interpolator circuit that uses a single DAC to manage multiple differential channels by employing a current source network and a thermometer-coded DAC architecture, allowing for phase interpolation across multiple channels with reduced hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate dedicated DAC is used for each CML channel, then phase accuracy and turn-on time are maintained, but device complexity and hardware cost increase
Solution Approach 1:
The patent merges multiple dedicated DACs into a single shared DAC that serves multiple CML channels. The phase interpolator circuit shares the DAC resource across different channels by time-multiplexing the phase adjustment function, thereby reducing the total number of DACs from N (one per channel) to 1, while maintaining phase accuracy through precise interpolator control
Solution Approach 2:
The single DAC is designed to perform multiple functions by serving different CML channels at different times. The phase interpolator enables the DAC to adjust phase for any of the multiple channels sequentially, making the DAC a universal component that replaces multiple channel-specific DACs, thus reducing hardware complexity without sacrificing reliability
2Measurement precision
If a separate dedicated DAC is used for each CML channel, then phase control precision is maintained, but the number of components and cost increase
Solution Approach 1:
Multiple DACs are merged into a single shared DAC that provides phase control for multiple CML channels. The phase interpolator circuit enables this single DAC to maintain precise phase control by interpolating between reference phases and adjusting the output phase accurately for each channel in sequence, thereby reducing the quantity of components from multiple DACs to one DAC while preserving phase control precision
Solution Approach 2:
The phase interpolator acts as an intermediary between the single shared DAC and the multiple CML channels. It receives the DAC output and performs precise phase interpolation to generate the required phase-shifted signals for different channels, thereby maintaining phase control precision even though only one DAC is used instead of multiple dedicated DACs
3Device complexity
If a shared DAC is used for multiple channels, then hardware complexity is reduced, but turn-on delay may increase
Solution Approach 1:
The phase interpolator circuit is designed with pre-charged nodes and anticipatory switching mechanisms that prepare the circuit state in advance before the actual phase transition is needed. This preliminary action reduces the effective turn-on delay by ensuring that capacitive nodes are pre-charged and switching elements are ready to transition quickly when required, compensating for the time-sharing nature of the shared DAC
Data Source
AI summary
A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated with phase signals. A bleeder current source is provided to generate a bleeder current, where the bleeder current is selected responsive to phase so the phase signals do not reach zero current.