Shared DAC Reference Routing to Prevent Voltage Contention

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Solution Overview

Problem

The placement of digital-to-analog converter (DAC) circuits on an integrated circuit (IC) to achieve uniform temperature distribution leads to variations in the shared reference voltage due to different routing impedances and equivalent resistances, causing voltage contention and conflict, especially when some DACs are powered down.

Innovation Solution

The implementation of a shared reference voltage generator circuit with individually routed traces configured with specific routing resistances based on expected or measured current loading from each DAC to ensure an equal voltage drop across these resistances, preventing voltage contention at the shared output node.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If multiple DACs share a common reference voltage to improve power efficiency, then energy consumption is reduced, but voltage contention and conflict occur at the shared output node due to different routing impedances and equivalent resistances

Engineering Contradiction:
Improvepower efficiencyVSAvoidvoltage stability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

A buffer circuit is introduced as an intermediary between the reference voltage source and multiple DACs. The buffer circuit isolates the shared reference voltage output from the varying load demands of individual DACs, preventing voltage contention while maintaining power efficiency. The buffer acts as a mediator that can supply different currents to different DACs without causing voltage conflicts at the shared node.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The reference voltage distribution network is segmented into individual routed traces for each DAC, with each trace having its own specified routing resistance. This segmentation allows each DAC to have a dedicated path with tailored impedance characteristics, eliminating voltage contention caused by shared routing while still sharing the common reference voltage source.

Inventive Principle:
Principle #1Segmentation

2Temperature

If DACs are located at various locations across the IC to achieve uniform temperature distribution, then thermal management is improved, but variations in reference voltage occur due to different routing impedances

Engineering Contradiction:
Improvetemperature uniformityVSAvoidreference voltage consistency
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

Each routed trace from the shared reference voltage output to individual DACs is designed with locally optimized resistance characteristics. The routing resistance of each trace is specifically specified to compensate for the unique path characteristics and load conditions of each DAC location, ensuring that each DAC receives the correct reference voltage despite being at different physical locations with different thermal environments.

Inventive Principle:
Principle #3Local quality

3Reliability

If individually routed traces are used to deliver reference voltage to each DAC, then voltage contention is avoided, but routing resistance variations cause unequal voltage drops

Engineering Contradiction:
Improvevoltage stabilityVSAvoidvoltage drop equality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The resistance parameter of each routed trace is specifically designed and adjusted based on the expected or measured current loading of the corresponding DAC. By changing the resistance parameter of each trace individually, the voltage drop across each trace is equalized, ensuring that all DACs receive the same reference voltage despite different current demands and physical locations.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures consistent reference voltage delivery to all DACs, even when they present different equivalent resistances or are in different operating states, thereby minimizing thermal gradients and maintaining accurate force/sense operations without DC cross-talk.

Implementation Method 1

reference voltage buffer circuitry, including an amplifier circuit, providing a commonly-routed amplifier shared output voltage node that is shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the first and second individually routed traces are configured with respective first and second routing resistances that are based on an expected or measured current loading from the corresponding DAC to provide an equal voltage drop across the first and second routing resistances

Methodology Applied
Scientific EffectOhm's law: Ohm's Law

Data Source

PatentUS10848172B2Forcing and sensing DACs sharing reference voltage
Publication Date: 2020.11.24 ANALOG DEVICES INT UNLTD CO
  • US10848172B2 patent drawing
  • US10848172B2 patent drawing

AI summary

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.