Shared-Data Processing Circuit for Hidden Dummy Operations

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Solution Overview

Problem

Existing data processing devices face challenges in efficiently implementing dummy operations to protect against physical attacks and side-channel analysis, as they require additional memory overhead and are vulnerable to fault attacks.

Innovation Solution

A data processing device that represents data words as shares and performs dummy operations using specific values, allowing for parallel processing and result sharing to mask real operations, thus hiding dummy operations without extra memory and detecting faults in dummy operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy calculations are introduced to protect against physical attacks, then security against side-channel analysis is improved, but memory overhead increases

Engineering Contradiction:
Improvesecurity against side-channel analysisVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The logic circuit is designed to perform both real cryptographic operations and dummy operations using the same hardware resources. The control sequence directs the circuit to execute dummy operations that consume the same computational resources and generate similar power consumption patterns as real operations, thereby providing security protection without requiring additional dedicated memory for dummy data storage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of storing actual dummy data in memory, the patent generates dummy operation inputs by copying and processing shares of cryptographic data through the same logic circuit. The dummy operations use copied shares that are processed identically to real shares, creating indistinguishable power consumption patterns without requiring separate dummy data storage.

Inventive Principle:
Principle #26Copying

2Reliability

If dummy operations are implemented with same behavior as real operations, then detection of dummy operations becomes difficult, but device complexity increases

Engineering Contradiction:
Improveindistinguishability of dummy operationsVSAvoidcontrol sequence complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system dynamically switches between real and dummy operations based on a control sequence. The logic circuit maintains the same operational behavior for both real and dummy operations, with the distinction being controlled by timing and control signals rather than structural differences. This dynamic approach allows dummy operations to be indistinguishable from real operations while managing complexity through control logic rather than hardware duplication.

Inventive Principle:
Principle #15Dynamics

3Reliability

If shares are used to represent data words, then security against fault attacks is improved, but processing complexity increases

Engineering Contradiction:
Improvesecurity against fault attacksVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments cryptographic data into multiple shares, where each share represents a portion of the original data. The logic circuit processes these shares independently through the same operational steps, and the final result is reconstructed by combining the processed shares. This segmentation provides fault attack resistance because a fault affecting one share does not compromise the entire cryptographic operation, while the processing complexity is managed by reusing the same circuit logic for each share.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12511434B2Data processing device and method for processing secret data
Publication Date: 2025.12.30 INFINEON TECHNOLOGIES AG
  • US12511434B2 patent drawing
  • US12511434B2 patent drawing
  • US12511434B2 patent drawing

AI summary

According to various embodiments, a data processing device is provided including a memory configured to represent each data word of a plurality of data words in the form of at least two respective shares, a logic circuit, an input circuit configured to provide input shares to the logic circuit depending on a control sequence specifying a sequence of real operations and dummy operations, wherein the logic circuit is configured to process the input shares to generate at least two processing result shares according to a predetermined logic function and an output circuit configured to output the at least two processing result shares if the control sequence specifies the current operation as a real operation and refresh the at least two shares of the one of the data words with the processing result shares if the control sequence specifies the current operation as a dummy operation.