Shared Data Line Read Write Circuit for Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in reducing power consumption, leakage current, and area occupancy in read and write circuits, which are typically separate and inefficient.
Innovation Solution
Combining read and write circuits into a single circuit, utilizing a sense amplifier for both operations, and implementing a smaller write logic block that leverages the existing sense amplifier structure to perform write operations, thereby reducing the need for separate write circuits and minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate read circuits and write circuits are used, then read and write operations can be performed independently, but power consumption and area occupancy increase
Solution Approach 1:
The patent combines separate read circuits and write circuits into a single shared circuit that can perform both read and write operations. The sense amplifier is configured to operate in different modes (read mode and write mode) by controlling the activation of specific transistors, eliminating the need for separate dedicated circuits for each operation.
Solution Approach 2:
The shared sense amplifier circuit is designed to perform multiple functions - both reading data from memory cells and writing data to memory cells. By using control signals to activate different transistor paths, the same hardware infrastructure supports both read and write operations, reducing overall circuit complexity and power consumption.
2Reliability
If separate read circuits and write circuits are used, then read and write operations can be performed independently, but area occupancy increases
Solution Approach 1:
The patent merges separate read and write circuit blocks into a single shared sense amplifier structure. This consolidation eliminates redundant circuitry and reduces the total area occupied by read/write interfaces in the memory device.
Solution Approach 2:
The shared circuit is designed with multi-functional capability, using control logic to switch between read and write operations. This universal approach allows one circuit to replace what would traditionally require two separate circuits, thereby reducing area occupancy.
3Ease of manufacture
If traditional write circuits are used, then write operations can be performed, but leakage current increases
Solution Approach 1:
The write operation uses periodic clock signals to control the timing of transistor activation. By enabling write transistors only during specific clock cycles and keeping them disabled otherwise, the circuit minimizes leakage current while maintaining full write operation capability when needed.
Data Source
AI summary
A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.