Shared Decoder Memory Architecture Reducing Die Area
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Solution Overview
Problem
Conventional memory devices with multiple banks require separate column select decoders and bit line sense amplifier control signals for each bank, leading to increased area and cost on memory dies.
Innovation Solution
A memory architecture that employs a shared global address decoder and latch-type local drive circuits, allowing multiple memory banks to be accessed independently with a shared set of control signals, reducing the need for separate decoders and amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate column select decoders and bit line sense amplifier control signals are used for each memory bank, then independent access capability is improved, but area and cost increase greatly
Solution Approach 1:
A single global column select decoder is designed to serve multiple memory banks simultaneously. The decoder receives bank select signals and column address signals, and generates column select signals that can be routed to any of the M memory banks, allowing one decoder to perform the function of M separate decoders.
Solution Approach 2:
A signal routing mechanism acts as an intermediary between the global column select decoder and the memory banks. This routing system directs the appropriate column select signals to the selected memory bank based on bank select signals, enabling shared decoder functionality while maintaining independent bank access.
2Adaptability or versatility
If separate column select decoders are used for each memory bank, then independent column selection is improved, but device complexity increases
Solution Approach 1:
The global column select decoder is designed with multi-functional capability to handle column selection for all M memory banks through a single unified structure, reducing the overall number of decoder circuits from M separate decoders to one shared decoder.
Solution Approach 2:
The decoder operation is segmented by bank select signals that divide the decoding process into bank-specific operations. The same physical decoder circuit is sequentially or concurrently activated for different banks based on the bank select signal, achieving independent column selection without requiring separate decoder hardware for each bank.
3Area of stationary object
If multiple memory banks share a global address decoder, then area reduction is improved, but access speed may be affected
Solution Approach 1:
Bank select signals are processed in advance to pre-configure the signal routing paths before column address decoding begins. This preliminary bank selection prepares the system to quickly route the decoded column select signals to the correct memory bank, minimizing access delay.
Solution Approach 2:
The signal routing system is designed to be dynamic,能够快速切换信号传输路径以适应不同的银行选择。通过动态路由机制，共享解码器可以在不同银行之间快速切换，保持高速访问性能。
Data Source
AI summary
A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.