Shared Main Decoding Circuit for Semiconductor Memory Banks

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Solution Overview

Problem

In semiconductor memory apparatuses with a stack bank structure, each memory bank requires a separate main decoding circuit due to differences in column selection lines, leading to increased load on the main decoding circuit.

Innovation Solution

A shared main decoding circuit that generates a shared column selection signal and uses a switching unit to selectively provide this signal to either the first or second memory bank based on a bank selection signal, allowing the same circuit to be used by multiple memory banks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate main decoding circuits are used for each memory bank, then each bank can operate independently, but the device complexity and load on decoding circuits increases

Engineering Contradiction:

Improveindependent bank operationVSAvoidnumber of decoding circuits

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple separate main decoding circuits into a single shared main decoding circuit that serves multiple memory banks. The shared circuit receives column address signals and generates column selection signals that are selectively applied to different banks through switching mechanisms, thereby reducing the total number of decoding circuits while maintaining independent bank operation capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The main decoding circuit is designed with multi-functionality to serve multiple memory banks. By incorporating switching units and control logic, the same decoding circuit can be dynamically allocated to different banks based on bank selection signals, enabling one circuit to perform the functions previously requiring multiple separate circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of operation

If separate main decoding circuits are used for each memory bank, then column selection can be performed independently, but the manufacturing cost and area increase

Engineering Contradiction:

Improveindependent column selectionVSAvoidmanufacturing cost and area

Core Design Contradiction:

Ease of operationVSEase of manufacture

Solution Approach 1:

The patent combines multiple decoding circuits into a shared resource that is time-multiplexed across different memory banks. Switching units enable the shared circuit to be connected to different banks sequentially, reducing the total silicon area and manufacturing cost while preserving independent column selection capability through controlled switching.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The system introduces dynamic switching mechanisms that allow the main decoding circuit to be flexibly allocated to different memory banks based on operational requirements. This dynamic reconfiguration enables area-efficient design while maintaining the functional independence needed for parallel bank operations.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8203903B2Main decoding circuit and semiconductor memory apparatus including the same

Publication Date: 2012.06.19 SK HYNIX INC

AI summary

A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column selection line of a first memory bank and a column selection line of a second memory bank in response to a bank selection signal.