Shared Decoupling Capacitors for PCB Noise Reduction
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Solution Overview
Problem
Conventional printed circuit boards lack an efficient design for connecting de-coupling capacitors between memory and microprocessor units, leading to signal integrity issues due to noise coupling from power supply components, and require an excessive number of capacitors to mitigate noise across long distances.
Innovation Solution
An electronic apparatus design where de-coupling capacitors are shared between a processor and memory, with a switch-controlled configuration to optimize noise reduction, utilizing a calculator to determine the minimum number of capacitors needed based on impedance and current information, and electromagnetic simulation to calculate accumulated noise values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If de-coupling capacitors are separately arranged for memory and MPU on conventional PCBs, then each component can be individually decoupled, but the number of capacitors increases and board area increases
Solution Approach 1:
The patent merges the de-coupling capacitor functions by placing capacitors on the lower surface that serve both the memory and MPU simultaneously. The capacitors are positioned to be electrically connected to both components through the PCB ground layers, reducing the total number of capacitors needed while maintaining power supply stability for both devices.
Solution Approach 2:
The de-coupling capacitors are designed to perform multiple functions by being accessible to both memory and MPU components. The PCB layout creates shared ground paths that allow the same capacitors to decouple noise for both devices, making the capacitor array universal rather than dedicated to a single component.
2Ease of manufacture
If memory and MPU are positioned at long-separated distances on PCB, then routing is simplified, but signal noise between components increases
Solution Approach 1:
The patent transitions from a planar PCB layout to a three-dimensional stacked configuration where memory and MPU are positioned on opposite surfaces of the PCB. This vertical stacking reduces the horizontal separation distance between components, minimizing signal noise while maintaining routing simplicity through organized layer structures.
3Object-affected harmful factors
If multiple de-coupling capacitors are arranged on lower surfaces of both memory and MPU, then power supply noise is suppressed, but device complexity increases
Solution Approach 1:
The patent combines the capacitor arrangements by placing capacitors on the lower PCB surface that serve both memory and MPU simultaneously. This shared capacitor configuration reduces the total number of capacitors needed compared to having separate capacitor arrays for each component, thereby reducing overall device complexity.
4Area of stationary object
If de-coupling capacitors are shared between memory and MPU, then PCB area is reduced, but noise suppression effectiveness may be compromised
Solution Approach 1:
The patent applies local quality by positioning shared de-coupling capacitors at specific locations on the lower PCB surface that are optimally close to both memory and MPU components. The capacitors are strategically placed near the component edges with direct ground connections, ensuring effective noise suppression for both devices while maintaining compact area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes signal integrity and power supply noise issues while reducing the number of de-coupling capacitors required, optimizing board size and signal transmission speed.
Implementation Method 1
The de-coupling capacitors play a role of a being stable suppliers of electric power to the MPU and the memory by utilizing the stored electric energy.
Implementation Method 2
at least one of the plurality of first terminals may connect to at least one of the plurality of second terminals through a via hole of the circuit board
Data Source
AI summary
An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed.