Shared Delay Circuit for Multi-Signal Area and Power Reduction
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Solution Overview
Problem
Conventional delay circuits experience significant area and power consumption increases as the number of input signals to be delayed grows, leading to inefficient operation and potential instability.
Innovation Solution
A delay circuit design that includes a delay unit generating a reference output signal, a storage unit for storing input signals, and an input/output count mechanism to manage signal delays, reducing the need for multiple shifters and stabilizing operations by using separate storage units for sequential signal activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple shifters are used to delay multiple input signals, then the delay function is achieved, but the circuit area increases in geometric progression
Solution Approach 1:
Multiple shifters that were previously used in parallel for different input signals are merged into a single shared shifter. The shifter is controlled by control signals that route the delayed output to different output lines based on which input signal needs delaying, thereby serving multiple input signals with one shifter unit and dramatically reducing circuit area.
Solution Approach 2:
The single shifter is designed to perform multiple functions by responding to different control signals. It can delay any of the multiple input signals as needed, making it a universal delay element that replaces multiple dedicated shifters, thus achieving the same delay functionality with reduced hardware.
2Reliability
If multiple shifters are used to delay multiple input signals, then the delay function is achieved, but power consumption increases
Solution Approach 1:
Multiple shifters that were previously used in parallel for different input signals are merged into a single shared shifter. The shifter is controlled by control signals that route the delayed output to different output lines based on which input signal needs delaying, thereby serving multiple input signals with one shifter unit and dramatically reducing circuit area.
Solution Approach 2:
The single shifter is designed to perform multiple functions by responding to different control signals. It can delay any of the multiple input signals as needed, making it a universal delay element that replaces multiple dedicated shifters, thus achieving the same delay functionality with reduced hardware.
3Adaptability or versatility
If the number of shifters increases, then more input signals can be delayed, but operation stability decreases
Solution Approach 1:
Multiple shifters that were previously used in parallel for different input signals are merged into a single shared shifter. The shifter is controlled by control signals that route the delayed output to different output lines based on which input signal needs delaying, thereby serving multiple input signals with one shifter unit and dramatically reducing circuit area.
Solution Approach 2:
The circuit employs control signal mechanisms that monitor which input signals require delaying and appropriately activate the shared shifter with correct control inputs. This feedback-based control ensures that only the necessary delay operations are performed, maintaining operational stability even as the number of supported input signals increases.
Data Source
AI summary
A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.