Shared Delay-Line Control for Clock and Command Phase Alignment
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Solution Overview
Problem
Conventional semiconductor apparatuses face phase differences between internal and external clocks due to clock transmission through buffers and transmission lines, requiring phase-locked loops or delay-locked loops for synchronization, which can be complex and inefficient.
Innovation Solution
A semiconductor apparatus with a shared shift register block that sets delay amounts for both clock and command delay lines to be substantially the same, using a delay line control block to generate control signals based on phase comparisons, allowing for efficient synchronization and data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple delay lines are controlled by separate shift registers, then each delay line can be independently adjusted, but the device complexity increases
Solution Approach 1:
The patent combines multiple separate shift registers into a single shared shift register block that controls multiple delay lines. This merging reduces the overall device complexity while maintaining the capability to independently adjust delay amounts for different delay lines through shared control resources.
Solution Approach 2:
The shared shift register block serves multiple functions by controlling multiple different delay lines (clock delay line, command delay line, etc.). This multi-functional design allows a single component to perform what previously required multiple separate components, thereby reducing complexity.
2Reliability
If phase compensation is implemented using conventional separate control blocks, then phase alignment can be achieved, but the synchronization process becomes complex
Solution Approach 1:
The patent merges multiple separate control blocks into an integrated delay line control block that manages phase compensation for multiple delay lines simultaneously. This integration simplifies the synchronization process while maintaining reliable phase alignment between internal and external clocks.
Solution Approach 2:
The delay line control block is designed as a universal control unit that can adjust delay amounts for multiple different types of delay lines (clock, command, etc.) through a unified control mechanism, thereby simplifying the overall control architecture.
Data Source
AI summary
A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.