Shared Delay Circuit for Read/Write Signal Timing
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Solution Overview
Problem
Conventional delay circuits in integrated circuits require multiple D-flip flops, leading to large area and power consumption due to the need for separate delay units for different signals, such as read and write commands, which is inefficient.
Innovation Solution
A delay circuit that shares configuration to delay multiple signals by using a delay unit, a signal type storing unit, and a transmitting unit to generate and transmit delayed signals based on stored signal types, reducing the need for multiple D-flip flops and thus minimizing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate delay units with multiple D-flip flops are used for different signals (read and write commands), then the delay function is achieved, but the area and power consumption increase
Solution Approach 1:
The patent merges multiple separate delay units into a single shared delay unit that processes multiple signals (read and write commands) sequentially. The delay unit is controlled by a select signal that determines which input signal to delay, eliminating the need for parallel delay circuits and reducing overall area
Solution Approach 2:
The single delay unit is designed to be universal by accepting multiple input signals (read command and write command) and producing delayed versions of whichever signal is selected. This multi-functional approach allows one circuit to replace multiple dedicated circuits, reducing area while maintaining the required delay functionality for different signal types
2Reliability
If separate delay units with multiple D-flip flops are used for different signals (read and write commands), then the delay function is achieved, but the power consumption increases
Solution Approach 1:
By combining multiple delay units into one shared resource, the patent reduces the total number of active circuit elements (D-flip flops) that consume power. Only one delay unit needs to be actively processing signals at any given time, controlled by the select signal, which reduces overall power consumption compared to having multiple simultaneously active delay units
3Reliability
If multiple D-flip flops are used in delay units, then the delay function is achieved, but the circuit complexity increases
Solution Approach 1:
The patent reduces circuit complexity by merging multiple independent delay units into a single unified delay unit with selection logic. Instead of having separate chains of D-flip flops for each signal type, the design uses one shared chain controlled by a select signal, simplifying the overall circuit architecture and reducing the number of interconnections
Data Source
AI summary
A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.