Shared-Die DRAM Stack for ECC and Die Failure Recovery
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Solution Overview
Problem
Existing memory systems face inefficiencies in data communication and reliability due to the lack of effective methods for managing multiple memory devices, particularly in stacked DRAM configurations, leading to potential failures and reduced performance.
Innovation Solution
A multi-channel memory stack architecture is introduced, utilizing a shared die for error correction and redundancy, where a shared die communicates data bursts after individual DRAM dies, and employs time-multiplexing and configurable command/address processing to optimize data transmission and replace failing dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DRAM dies are stacked in a memory system, then memory capacity and bandwidth are improved, but reliability and error correction capability deteriorate
Solution Approach 1:
The patent segments the memory system into multiple independent DRAM dies (first set and second set) coupled to different memory channels, with each die operating semi-independently. This segmentation allows the system to maintain high bandwidth through parallel operations while isolating errors to specific dies or channels, thereby preserving overall reliability.
Solution Approach 2:
The patent introduces a shared die that acts as an intermediary between the first and second sets of DRAM dies. This shared die provides error correction codes (ECC) and redundancy information that protect data from both sets of dies, enabling the system to correct errors without sacrificing bandwidth performance.
2Reliability
If a shared die is added for error correction, then reliability is improved, but device complexity increases
Solution Approach 1:
The shared die is designed to serve multiple functions: it provides error correction for both the first and second sets of DRAM dies, acts as a backup storage location for redundancy information, and can replace failed dies. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the error correction and redundancy functions into a single shared die that is commonly used by both memory channels. Instead of having separate ECC mechanisms for each channel, the shared die consolidates these functions, reducing overall system complexity while maintaining reliability.
3Productivity
If time-multiplexing is used for data bursts, then data communication efficiency is improved, but processing delay increases
Solution Approach 1:
The patent implements time-multiplexing where the shared die communicates data bursts in periodic intervals after the individual DRAM dies have completed their transmissions. This periodic action allows efficient use of the data interface without creating continuous delays, as the shared die operates in structured time slots that optimize throughput.
Solution Approach 2:
The individual DRAM dies in the first and second sets complete their data bursts first, preparing the data interface in advance. The shared die then uses this pre-prepared interface for its error correction and redundancy data transmission. This preliminary action by the individual dies minimizes the additional delay introduced by the shared die's operations.
Data Source
AI summary
An interconnected stack of Dynamic Random Access Memory (DRAM) die has a first set of DRAM die (e.g., two, three, four, etc.) coupled to a first independent memory channel, a second set of DRAM die (e.g., two, three, four, etc.) coupled to a second independent memory channel, and a shared die coupled to both independent memory channels. The shared die may be used to store information (e.g., error correcting code) for Reliability, Availability, and Serviceability (RAS) purposes. The shared die may also be used to replace the functionality of a failed or failing die.