Shared Dielectric Layer for Medium-Voltage Transistor Fabrication
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Solution Overview
Problem
Conventional processes for fabricating medium-voltage transistors are costly due to dedicated steps required for each type of transistor, particularly for medium-voltage and high-voltage devices, which increases the overall cost of integrated circuits.
Innovation Solution
A process where the fabrication of medium-voltage transistors shares common steps with floating-gate transistors, specifically using a common dielectric layer and gate region formation to reduce costs, allowing the production of medium-voltage transistors at zero additional cost by leveraging existing steps in the floating-gate transistor process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated implanting steps and oxide formation steps are used for each type of transistor, then the transistor performance and voltage range are improved, but the manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent applies universality by making the tunnel dielectric layer serve dual functions: as the tunnel dielectric for floating-gate transistors and as the gate dielectric for medium-voltage transistors. This eliminates the need for separate dedicated oxide formation steps for medium-voltage transistors, reducing process complexity while maintaining transistor performance. The same implanting steps that create the floating-gate region also create the gate region for medium-voltage transistors.
Solution Approach 2:
The patent merges previously separate fabrication processes by combining the formation of medium-voltage transistors and floating-gate transistors into a single integrated process flow. The tunnel dielectric layer formation, floating-gate region implantation, and gate region formation are all performed in common steps, significantly reducing the total number of manufacturing steps required.
2Manufacturing precision
If dedicated processing steps are provided for each transistor type, then the manufacturing precision and voltage range coverage are improved, but the overall manufacturing cost increases
Solution Approach 1:
The tunnel dielectric layer is designed with specific thickness and material properties that enable it to function as gate dielectric across a broad voltage range (1.8V to 5V). This universal gate dielectric structure eliminates the need for separate dedicated oxide formation steps for different voltage ranges, reducing manufacturing cost while maintaining precision voltage range coverage through single-step fabrication.
Solution Approach 2:
The patent utilizes parameter changes in the tunnel dielectric layer thickness and material composition to achieve both high manufacturing precision for voltage range coverage and cost-effectiveness. By optimizing the tunnel dielectric parameters during a common fabrication step, the process achieves precise control over transistor voltage characteristics without requiring multiple dedicated processing steps.
3Reliability
If separate gate oxide formation steps are used for medium-voltage and floating-gate transistors, then the electrostatic control and device reliability are improved, but the process time and productivity are reduced
Solution Approach 1:
The patent merges the gate oxide formation step for medium-voltage transistors with the tunnel dielectric formation step for floating-gate transistors into a single common process step. This eliminates redundant processing time while maintaining the electrostatic control required for reliable transistor operation, as both transistor types share the same gate dielectric structure.
Solution Approach 2:
The continuous formation of the tunnel dielectric layer serves both transistor types simultaneously in an uninterrupted process flow. This continuous useful action maintains electrostatic control for both medium-voltage and floating-gate transistors while maximizing productivity by eliminating idle time between separate formation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the overall cost of integrated circuits, improves electrostatic control, reduces channel pinch-off effects, and lowers leakage currents while broadening the range of applicable medium voltages, resulting in more robust and efficient transistor performance.
Implementation Method 1
tunnel-dielectric layer of the floating-gate transistor, which layer is intended to allow transfer of charge via the Fowler-Nordheim effect at second voltages higher than the first supply voltage, for example higher than 10 V
Data Source
AI summary
A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.