Shared Diffusion Layer Transistors for Interconnect Resistance
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Solution Overview
Problem
In semiconductor devices, the separation of functional circuit and driver regions leads to increased layout areas and long interconnect distances, resulting in insufficient suppression of interconnect resistance, which causes waveform distortion and limits the speed of circuit operations, especially when power gating is employed to reduce subthreshold current.
Innovation Solution
The use of transistors with shared diffusion layers and optimized gate electrode configurations allows for reduced interconnect resistance by eliminating the need for interconnects between drain and source regions, and by strategically placing SCRC drivers between final and front stage transistors, thereby minimizing layout area and interconnect resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If functional circuit and driver regions are separated, then layout area increases, but interconnect resistance cannot be sufficiently suppressed
Solution Approach 1:
The patent merges the functional circuit region and driver region into a unified layout where SCRC drivers are strategically placed within or adjacent to the functional circuit region. This integration eliminates the need for long interconnects between separated regions, reducing interconnect resistance while maintaining compact layout area.
2Length of moving object
If interconnect length between circuit cell and SCRC driver is large, then interconnect resistance increases, but waveform distortion occurs
Solution Approach 1:
The patent employs preliminary action by strategically pre-positioning SCRC drivers within close proximity to circuit cells before interconnect routing is designed. This advance placement ensures that interconnect length is minimized from the outset, preventing waveform distortion before it can occur during circuit operation.
3Loss of energy
If power gating is used to reduce subthreshold current, then consumption current decreases, but interconnect resistance becomes more critical
Solution Approach 1:
The patent applies local quality by implementing power gating selectively in specific circuit regions while maintaining low interconnect resistance through localized SCRC driver placement. This approach allows consumption current to be reduced in standby regions without suffering from high interconnect resistance, as the low-resistance paths are established locally where needed.
Data Source
AI summary
A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first direction, and a first connecting electrode portion extending in a second direction approximately orthogonal to the first direction and connecting one ends of the first and second parallel electrode portions to each other, and first and second diffusion layers separated from each other by a channel region under the first gate electrode, a first output line connected to the first diffusion layer of the first transistor, and a second transistor comprising a second gate electrode extending in the second direction, and the second transistor being configured to use the second diffusion layer of the first transistor as one of two diffusion layers that are separated from each other by a channel region under the second gate electrode.