Shared Disturbance Circuitry for Memory Section Coupling
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Solution Overview
Problem
Existing memory devices face challenges with usage-based disturbance, leading to memory errors and data loss due to electromagnetic coupling between adjacent memory cells, which increases complexity, cost, and power consumption, making it difficult to integrate in space-constrained devices.
Innovation Solution
Implementing sharable usage-based disturbance circuitry that includes shared counter circuits and error-correction-code circuits across multiple sections of a memory device's die, reducing footprint, power consumption, and complexity by managing disturbance across multiple sections with a single set of circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate disturbance circuits are implemented for each memory section, then disturbance mitigation reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple separate disturbance circuits into a single shared disturbance circuit that serves multiple memory sections. The shared circuit includes a disturbance detector that monitors multiple sections and a disturbance mitigation component that applies correction signals to affected sections, thereby reducing overall device complexity while maintaining disturbance mitigation capability across all sections.
Solution Approach 2:
The shared disturbance circuit is designed with multi-functional capability to handle disturbance detection and mitigation for multiple memory sections simultaneously. The disturbance detector can identify disturbances in any monitored section, and the mitigation component can apply corrections to any affected section, making the circuit universal rather than section-specific.
2Reliability
If separate disturbance circuits are implemented for each memory section, then disturbance mitigation reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple separate disturbance circuits into a single shared disturbance circuit that serves multiple memory sections. The shared circuit includes a disturbance detector that monitors multiple sections and a disturbance mitigation component that applies correction signals to affected sections, thereby reducing overall device complexity while maintaining disturbance mitigation capability across all sections.
3Reliability
If separate disturbance circuits are implemented for each memory section, then disturbance mitigation reliability is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple separate disturbance circuits into a single shared disturbance circuit that serves multiple memory sections. The shared circuit includes a disturbance detector that monitors multiple sections and a disturbance mitigation component that applies correction signals to affected sections, thereby reducing overall device complexity while maintaining disturbance mitigation capability across all sections.
4Reliability
If more disturbance circuits are implemented, then disturbance mitigation capability is improved, but signal routing complexity increases
Solution Approach 1:
The shared disturbance circuit acts as an intermediary between multiple memory sections and the disturbance mitigation system. The disturbance detector monitors multiple sections through this intermediary, and the mitigation component applies corrections through the same intermediary, simplifying signal routing compared to direct connections from separate circuits to each section.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, power consumption, and simplifies signal routing, while enhancing the reliability of memory devices by effectively mitigating usage-based disturbance and improving data integrity.
Implementation Method 1
usage-based disturbance, leading to memory errors and data loss due to electromagnetic coupling between adjacent memory cells
Data Source
AI summary
Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.