Shared DLL Clock Routing for DDR5 DQ Timing Synchronization
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Solution Overview
Problem
As the number of memory banks in semiconductor devices increases, there is a need to reduce the size and power consumption of components used for delay-locked loop (DLL) clock signals, which are crucial for proper timing and synchronization of internal command and clock signals in memory devices, while maintaining efficacy.
Innovation Solution
The solution involves selectively providing a delay-locked loop clock signal to a DQ system by combining logic among multiple DQ pads, reducing the complexity of the DLL routing system and overall power consumption, and minimizing the layout area used for DLL distribution circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory banks is increased, then the memory capacity and functionality are improved, but the power consumption and layout area of DLL distribution circuitry increase
Solution Approach 1:
Multiple DQ pads share a common DLL distribution circuitry through a multiplexer, combining what would traditionally be separate DLL circuits into a shared resource. This merging approach reduces the total power consumption and layout area while supporting multiple memory banks.
Solution Approach 2:
The DLL distribution circuitry is designed to serve multiple DQ pads through time-multiplexed operation. A single DLL circuit performs the function of multiple DLL circuits by sequentially serving different DQ pads, making the circuit universal rather than dedicated to a single pad.
2Quantity of substance
If the number of memory banks is increased, then the memory capacity and functionality are improved, but the layout area of DLL distribution circuitry increases
Solution Approach 1:
Multiple DQ pads share a common DLL distribution circuitry through a multiplexer, combining what would traditionally be separate DLL circuits into a shared resource. This merging approach reduces the total power consumption and layout area while supporting multiple memory banks.
Solution Approach 2:
The patent transitions from a spatial distribution of multiple DLL circuits (one per DQ pad) to a temporal distribution using a single DLL circuit served by a multiplexer. This dimensional change from space to time reduces the layout area required.
3Measurement precision
If separate DLL circuits are provided for each DQ pad, then the timing precision and synchronization are improved, but the device complexity and power consumption increase
Solution Approach 1:
Multiple DQ pads share a common DLL distribution circuitry through a multiplexer, combining what would traditionally be separate DLL circuits into a shared resource. This merging approach reduces the total power consumption and layout area while supporting multiple memory banks.
Solution Approach 2:
A multiplexer is introduced as an intermediary component that selectively connects the single DLL circuit to different DQ pads. This intermediary enables time-multiplexed operation, reducing complexity while maintaining timing precision through controlled signal distribution.
4Measurement precision
If separate DLL circuits are provided for each DQ pad, then the timing synchronization is improved, but the power consumption increases
Solution Approach 1:
Multiple DQ pads share a common DLL distribution circuitry through a multiplexer, combining what would traditionally be separate DLL circuits into a shared resource. This merging approach reduces the total power consumption and layout area while supporting multiple memory banks.
Solution Approach 2:
The single DLL circuit operates periodically, sequentially serving different DQ pads in a time-multiplexed manner. This periodic operation reduces power consumption compared to having multiple continuously operating DLL circuits, while maintaining timing synchronization through controlled periodic signal distribution.
Data Source
AI summary
An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.