Shared DLL Core for DRAM Controller Signal Delay Stability

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Solution Overview

Problem

Existing DRAM controllers face inefficiencies and increased costs due to the need for multiple delay locked loops (DLLs) to maintain constant signal delays over process, voltage, and temperature variations, leading to higher system costs and lower performance during read operations.

Innovation Solution

A dynamic random access memory (DRAM) controller utilizing a shared DLL core and control circuit that dynamically updates delay values based on operational modes, allowing the DLL to lock during read cycles using the memory data strobe signal and during other cycles using the processor clock signal, thereby reducing the need for duplicate DLLs and minimizing system performance interruptions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple DLLs are used to maintain constant signal delays during read operations, then signal delay stability is improved, but system cost and device complexity increase

Engineering Contradiction:

Improvesignal delay stabilityVSAvoidnumber of DLLs

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple DLLs into a single shared DLL core that is dynamically allocated to serve both read operations and other operations (write, refresh, self-refresh). The DLL core is shared across different operational modes, eliminating the need for duplicate DLL instances while maintaining signal delay stability through dynamic reconfiguration.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared DLL core is designed to be universal, serving multiple functions across different operational modes. It can function as a read DLL, write DLL, or refresh DLL depending on the operational state of the DRAM controller, thereby reducing the total number of DLLs required in the system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If duplicate DLLs are implemented to maintain lock during read operations, then system performance is improved, but circuit area and power consumption increase

Engineering Contradiction:

Improvesystem performanceVSAvoidcircuit area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic allocation of the shared DLL core to different operational modes based on real-time system state. The DLL core dynamically switches between serving read operations, write operations, and refresh operations, optimizing circuit area utilization while maintaining system performance through timely reconfiguration.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The DLL core periodically reconfigures itself to serve different operational modes. During read operations, it locks to the DQS signal; during other operations, it locks to the reference clock signal. This periodic reconfiguration allows a single DLL core to replace multiple dedicated DLLs, reducing circuit area while maintaining performance.

Inventive Principle:

Principle #19Periodic action

3Device complexity

If a single shared DLL is used for multiple operations, then device complexity is reduced, but the ability to maintain lock during simultaneous operations deteriorates

Engineering Contradiction:

Improvenumber of DLLsVSAvoidlock maintenance capability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent changes the operational parameters of the shared DLL core based on the current system state. The DLL core dynamically adjusts its reference signal source (DQS signal during read operations, reference clock signal during other operations) and its operational mode to maintain lock capability across different operational contexts while serving multiple functions.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system implements feedback control to monitor the operational state of the DRAM controller and dynamically reconfigure the shared DLL core accordingly. The feedback mechanism ensures that the DLL core maintains proper lock to the appropriate reference signal based on current operations, preserving reliability while using a single shared instance.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7869287B2Circuit for locking a delay locked loop (DLL) and method therefor

Publication Date: 2011.01.11 ADVANCED MICRO DEVICES INC

AI summary

A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.