Shared DLL Timing Control for DRAM Read and Write Paths
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Solution Overview
Problem
The high cost, large physical size, and significant electrical power consumption of delay locked loop (DLL) circuits in DRAM controllers make them expensive and inefficient, limiting system performance and increasing operating costs due to the need for multiple delays in read and write operations.
Innovation Solution
A shared DLL is used for both read and write paths in a DRAM controller, dynamically updating delay values based on the current operation cycle, reducing the number of required DLLs and optimizing circuit area and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate DLL circuits are used for read and write paths, then timing accuracy for each operation is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines separate DLL circuits for read and write paths into a single shared DLL circuit. The DLL is configured to operate in different modes (read mode and write mode) depending on the operational phase, allowing one circuit to perform multiple functions that previously required separate circuits, thereby reducing overall device complexity while maintaining timing accuracy through mode-specific configuration
Solution Approach 2:
The shared DLL circuit is designed with multi-functionality to serve both read and write operations. By implementing mode selection logic and configurable delay parameters, the single DLL circuit can adapt its behavior to meet the specific timing requirements of either read or write operations, eliminating the need for dedicated separate circuits
2Measurement precision
If multiple DLL circuits are used for read and write operations, then timing control for each operation is improved, but manufacturing yield decreases
Solution Approach 1:
By merging multiple DLL circuits into a single shared circuit, the patent reduces the total number of components that need to be manufactured and tested. This consolidation increases manufacturing yield by eliminating potential failure points associated with multiple separate circuits while maintaining precise timing control through the shared circuit's mode-specific operation
3Measurement precision
If separate DLL circuits are used for read and write paths, then timing accuracy is improved, but silicon area increases
Solution Approach 1:
The patent merges separate DLL circuits into a single shared circuit, directly reducing the silicon area occupied by delay locked loop components. The shared DLL maintains timing accuracy for both read and write operations by switching between modes and adjusting delay parameters accordingly, achieving area efficiency without sacrificing timing precision
Solution Approach 2:
The shared DLL circuit implements multi-functionality to serve both read and write paths, allowing one circuit to replace what would traditionally require multiple separate circuits. This universal design significantly reduces the silicon footprint while maintaining the timing accuracy required for different operational modes through configurable parameters
4Measurement precision
If multiple DLL circuits are used, then timing delays for read and write operations are optimized, but power consumption increases
Solution Approach 1:
By combining multiple DLL circuits into a single shared circuit, the patent reduces the total power consumption associated with DLL operation. The shared circuit consumes power for only one operation at a time, switching between read and write modes as needed, whereas separate circuits would continuously consume power regardless of operational phase, thereby reducing overall energy usage while maintaining optimized timing delays
Data Source
AI summary
A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.