Shared DMAC and Module Arbiter for Image Processing Bus Arbitration
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Solution Overview
Problem
In image processing apparatuses, the use of multiple DMACs increases chip area and reduces memory access efficiency due to frequent bus requests and inefficient memory access patterns, particularly when accessing macroblocks in DRAM.
Innovation Solution
An image processing apparatus with a shared DMAC and a module arbiter that manages memory access through a bus, utilizing burst transfers and buffers to optimize data transfer, reducing the number of DMACs and improving bus bandwidth efficiency by arbitrating read and write requests and aligning data transfers with bus widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated DMACs are provided for each module core, then memory access capability is improved, but chip area increases
Solution Approach 1:
The patent merges multiple dedicated DMACs into a single shared DMAC that serves multiple module cores. The DMAC is shared between a first module core and a second module core, eliminating the need for separate DMAC instances for each core while maintaining memory access functionality through arbitration.
Solution Approach 2:
The patent introduces a bus arbiter as an intermediary component that mediates access to the shared DMAC between multiple module cores. The arbiter manages contention for the shared resource, allocating DMAC access rights to different cores based on arbitration logic, thereby enabling efficient sharing without direct conflicts.
2Adaptability or versatility
If access to DRAM is performed on macroblock unit, then processing granularity is improved, but memory access efficiency decreases
Solution Approach 1:
The patent segments the macroblock processing into smaller line units. Instead of accessing entire macroblocks (e.g., 16x16 pixels) as single units, the system processes and transfers data line by line (e.g., 8 bytes per line in YUV422 format), allowing finer-grained control and more efficient memory access patterns that align with DRAM row structure.
Solution Approach 2:
The patent performs preliminary actions by pre-fetching and buffering data in advance. The interface circuit includes buffers that store data read from the image supply source memory, and the system reads multiple lines in advance to fill these buffers, reducing the frequency of memory access requests and improving overall access efficiency.
3Reliability
If read request is issued every line of macroblock, then data freshness is improved, but bus bandwidth consumption increases
Solution Approach 1:
The system performs preliminary data loading by reading multiple lines in advance and storing them in buffers before they are needed for processing. This pre-fetching strategy ensures that data is ready when needed (maintaining data freshness) while reducing the frequency of bus access requests, as multiple lines are loaded in batch operations rather than one line at a time.
Solution Approach 2:
The patent implements continuous data transfer operations where the DMAC performs burst transfers of multiple lines consecutively without interrupting the bus. By maintaining continuous transfer actions and avoiding frequent start-stop cycles of individual line requests, the system reduces overhead and improves bus utilization efficiency while ensuring data availability.
Data Source
AI summary
An image processing apparatus includes a plurality of image processing module parts, a module arbiter part, and a DMAC (Direct Memory Access Controller) part. Each of the image processing module parts includes a module core for executing a predetermined image processing. The plurality of image processing module parts is connected to the module arbiter part. The module arbiter part arbitrates memory access which is given by the plurality of image processing module parts through a bus. The DMAC part is connected between the module arbiter part and the bus, and executes memory access related to the arbitration result obtained by the module arbiter part.