Shared DQ Channel Signaling for Concurrent Data and Command Transfer
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Solution Overview
Problem
The data input/output efficiency of non-volatile memories connected to a shared channel is compromised due to the high transmission rate of data and the low transmission rate of commands, leading to reduced real-time processing capabilities as storage device capacity increases.
Innovation Solution
A method and system for a storage device that allows simultaneous transmission of data and embedded commands in both directions of a channel, using a memory controller with data extraction, command logic, and switch circuits to manage the data and command signals on a shared data signal line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted at a high transmission rate through the shared DQ line, then data transmission speed is improved, but command transmission rate becomes relatively low, reducing overall data input/output efficiency
Solution Approach 1:
The patent combines data and command transmissions into a single shared DQ line, allowing both types of signals to coexist on the same physical medium. The memory controller and memory devices use voltage level differentiation to distinguish between data and command signals, enabling simultaneous transmission without requiring separate dedicated lines for each signal type.
Solution Approach 2:
The patent utilizes voltage level parameter changes to encode different types of information on the same signal line. Data signals use voltage levels relative to a first reference voltage, while command signals use voltage levels relative to a second reference voltage. This parameter differentiation allows the system to multiplex multiple signal types over a single channel, resolving the contradiction between high-speed data transmission and efficient command transmission.
2Device complexity
If multiple non-volatile memories are connected to a single shared channel, then device complexity is reduced, but data input/output efficiency decreases due to serial transmission requirements
Solution Approach 1:
The shared DQ line is designed to serve multiple functions simultaneously: it can transmit data from any connected memory device to the memory controller, transmit commands from the memory controller to any memory device, and support bidirectional communication. This multi-functional design allows multiple memory devices to share a single channel without requiring complex dedicated wiring for each device.
Solution Approach 2:
The memory controller acts as an intermediary that manages communication between multiple memory devices and the external system. It interprets voltage levels to distinguish between data and commands, routes signals appropriately, and coordinates transmissions to ensure efficient data input/output operations across all connected memory devices through the shared channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data input/output efficiency by enabling the concurrent transmission of data and commands, thereby improving real-time processing capabilities and data transmission speed in storage devices with increasing capacities.
Implementation Method 1
a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line
Data Source
AI summary
A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.