Shared DQS Enable Signal for Memory Interface Timing
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Solution Overview
Problem
Conventional DDR memory interface implementations face challenges in accurately gating the DQS signal to prevent spurious signals, particularly due to tri-stated periods, and fail to compensate for duty cycle distortion variations affecting timing windows, leading to inefficiencies and potential errors in data transfer.
Innovation Solution
A clock-like DQS enable signal is used to enable both falling and rising edge detection, reducing circuit duplication and allowing for more efficient sampling, which compensates for duty cycle distortion variations, thereby improving timing accuracy and reducing silicon area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple DQS edges are sampled utilizing a free running clock, then timing accuracy is improved, but device complexity increases due to significant circuit duplication to provide phase control
Solution Approach 1:
The patent merges the gating function and sampling function into a single shared enable signal path. The same signal that gates the DQS input also serves as the sampling clock for the flip-flop, eliminating the need for separate free-running clock circuitry and phase control logic that would otherwise be required to sample multiple DQS edges accurately.
Solution Approach 2:
The enable signal is given multiple functions: it serves as both the gating control signal for the DQS input and the sampling clock signal for the flip-flop. This multi-functional approach eliminates the need for separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining timing accuracy.
2Device complexity
If only the rising edge of the DQS signal is tracked, then circuit complexity is reduced, but performance deteriorates because duty cycle distortion variation is not compensated
Solution Approach 1:
The patent implements feedback by sampling both rising and falling edges of the DQS signal and using this information to adjust the enable signal timing. The sampled edges are fed back to a counter that tracks the position of DQS transitions, and this tracking information is used to dynamically adjust the enable signal to compensate for duty cycle distortion variations, thereby improving reliability without significantly increasing complexity.
Data Source
AI summary
In a memory interface circuit (e.g., a programmable logic device), a clock or strobe (DQS) signal can be gated using a clock-like signal that can also be used to sample the DQS signal. Furthermore, both the rising and falling edges of the DQS signal can be sampled using the clock-like signal.