Shared-Drain Back-to-Back LDMOS Load Switch Layout for Lower Rsp
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Solution Overview
Problem
Existing high voltage load switches using back-to-back connected LDMOS devices quadruple the specific-on-resistance (Rsp) due to doubled device area and on-resistance, making them inefficient and costly for integrated circuits.
Innovation Solution
A load switch design featuring shared-drain transistors with back-to-back connected LDMOS devices, where the transistors share a drain and have a high voltage oxide region, reducing unnecessary drain regions to minimize spacing and area, thereby improving Rsp efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If back-to-back connected LDMOS devices are used to achieve bidirectional current blocking, then current blocking capability is improved, but specific-on-resistance increases by 4 times
Solution Approach 1:
The patent merges two LDMOS devices into a shared-drain configuration where the drain regions are combined and shared between both transistors. This merging reduces the total device area and minimizes the number of unnecessary drain regions, thereby reducing the specific-on-resistance by 27% while maintaining bidirectional current blocking capability through the back-to-back connection architecture.
2Reliability
If back-to-back connected LDMOS devices are used to achieve bidirectional current blocking, then current blocking capability is improved, but device area increases
Solution Approach 1:
The patent merges two LDMOS devices into a shared-drain configuration where the drain regions are combined and shared between both transistors. This merging reduces the total device area by eliminating redundant drain regions and minimizing the spacing between transistors, achieving a more compact footprint while maintaining bidirectional current blocking capability.
Solution Approach 2:
The patent optimizes the spatial arrangement of the shared-drain transistors by minimizing the spacing between them in the planar dimension. By carefully designing the layout to reduce the distance between adjacent transistors and utilizing the vertical dimension for gate structures, the device achieves reduced footprint area while maintaining electrical performance.
3Device complexity
If conventional LDMOS devices are used, then device structure is simple, but Rsp efficiency is poor
Solution Approach 1:
The patent merges two LDMOS devices into a shared-drain configuration where the drain regions are combined and shared between both transistors. This merging reduces the total device area and minimizes the number of unnecessary drain regions, thereby reducing the specific-on-resistance by 27% while maintaining bidirectional current blocking capability.
Data Source
AI summary
An apparatus includes a first drain/source region and a second drain/source region over a substrate, and a first gate adjacent to the first drain/source region and a second gate adjacent to the second drain/source region, wherein the first gate and the second gate are separated from each other, wherein the first drain/source region, the second drain/source region, the first gate and the second gate form two back-to-back connected transistors.