Shared Driver Circuitry for MIPI C-PHY and D-PHY Interface
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Solution Overview
Problem
Conventional electronic systems lack shared interface circuitry that can support both D-PHY and C-PHY protocols, making it challenging to design systems that can efficiently handle both driving modes without area or speed penalties.
Innovation Solution
A shared driver structure is implemented, utilizing half-driver sub-circuits that can be configured to operate in both D-PHY and C-PHY modes, allowing for the same set of serializers to be reused in both driving modes without additional pins or increased loading on shared pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate D-PHY and C-PHY transceiver components are used, then protocol support is complete, but hardware area and device complexity increase
Solution Approach 1:
The patent implements a universal transceiver architecture where a single physical interface circuit can operate in both D-PHY and C-PHY modes. The same driver circuits, equalization blocks, and data paths are configured differently to support both protocols, eliminating the need for separate dedicated hardware for each protocol and reducing overall device complexity while maintaining full protocol support
Solution Approach 2:
The transceiver incorporates dynamic configuration capabilities where circuit elements can be reconfigured between D-PHY and C-PHY modes through control signals. The driver strength, equalization settings, and data path parameters are dynamically adjusted based on the selected protocol mode, enabling a single static hardware structure to adapt to different protocol requirements
2Adaptability or versatility
If separate D-PHY and C-PHY transceiver components are used, then protocol support is complete, but power consumption increases
Solution Approach 1:
By implementing a single universal transceiver that can operate in both D-PHY and C-PHY modes, the patent eliminates the need to power two separate transceiver chains. The same hardware resources are shared between protocols, reducing overall power consumption while maintaining the ability to support both protocols when needed
Solution Approach 2:
The patent extracts the common functional elements (drivers, equalization, data paths) that are shared between D-PHY and C-PHY protocols, separating them from protocol-specific elements. This allows the shared infrastructure to be powered and configured only when needed, reducing idle power consumption compared to having always-active separate transceivers
3Adaptability or versatility
If additional pins are added for C-PHY mode, then protocol functionality is complete, but pin count and loading on shared pins increase
Solution Approach 1:
The patent designs the physical interface pins to serve dual purposes for both D-PHY and C-PHY protocols. The same set of pins is configured differently through control logic to support the specific signal requirements of each protocol, eliminating the need for additional dedicated pins and reducing the overall pin count while maintaining full protocol functionality
Solution Approach 2:
The pin configuration is dynamically controlled based on the active protocol mode. Control signals reconfigure the electrical characteristics and signal routing of the shared pins to match the requirements of either D-PHY or C-PHY, enabling a static pin set to fulfill dynamic protocol-specific requirements
Data Source
AI summary
Imaging circuitry may include half-driver sub-circuits configured to support Mobile Industry Processor Interface (MIPI) D-PHY mode and C-PHY mode. Groups of two half-driver sub-circuits can be coupled together in the D-PHY mode, whereas groups of three half-driver sub-circuits can be coupled together in the C-PHY mode. Each half-driver sub-circuit can include one or more pull-up paths and one or more pull-down paths. Each half-driver sub-circuit can include multiple slices, a first portion of which can be operated to pull in a first direction and a second portion of which can be operated to pull in a second direction opposing the first direction to achieve the desired amount of equalization. The half-driver sub-circuits can be employed as the final driver stage of a shared data path architecture supporting both D-PHY and C-PHY modes. The shared data path can include serializers, pre-driver logic, and/or equalization enable blocks.