Shared Driver Testing Apparatus for DRAM and Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional testing apparatuses require longer times to test high-access-speed devices like DRAM and low-access-speed devices like flash memory in parallel, leading to idle time due to sequential testing, which reduces operational efficiency and increases processing time.
Innovation Solution
A testing apparatus with a control device and device interface section that switches test signals and reference voltages between DRAM and flash memory terminals, allowing simultaneous testing by sharing test signal generating sections and drivers, and using switches and DA converters to manage voltage levels for stable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate testing units are used for DRAM and flash memory, then each device can be tested independently, but the testing apparatus requires more testing units and remains idle during sequential testing
Solution Approach 1:
The patent applies universality by designing a single testing unit that can function for both DRAM and flash memory devices. The testing unit includes reconfigurable components (switches, drivers, signal generators) that can be dynamically assigned to different device types, allowing one unit to replace multiple dedicated units while maintaining testing accuracy for each device type.
Solution Approach 2:
The patent implements dynamics through time-division multiplexing where the testing unit dynamically switches between testing DRAM and flash memory devices. The switch control section dynamically reconfigures the testing unit's connections and parameters based on which device type is being tested, enabling the unit to adapt its function over time rather than being statically dedicated to one device type.
2Reliability
If testing is performed sequentially for different device types, then each device receives dedicated testing resources, but idle time increases and productivity decreases
Solution Approach 1:
The patent achieves continuity of useful action by eliminating idle time between testing different device types. The testing unit is continuously engaged in testing operations, dynamically switching between DRAM and flash memory devices without remaining idle. The switch control section ensures seamless transitions between device types, maintaining continuous productive operation of the testing unit.
Solution Approach 2:
The patent implements periodic action through time-division multiplexing where the testing unit alternates between testing DRAM and flash memory devices in periodic cycles. The switching between device types follows a structured periodic pattern controlled by the switch control section, allowing the unit to systematically serve multiple device types while maintaining continuous operation.
3Productivity
If multiple testing units operate in parallel, then processing time is reduced, but device complexity and cost increase
Solution Approach 1:
The patent applies merging by combining the testing resources for DRAM and flash memory into a single integrated testing unit. Instead of maintaining separate parallel testing units for each device type, the patent merges the signal generators, drivers, switches, and control logic into one unified unit that can handle both device types, reducing overall system complexity while maintaining parallel testing capability through time-division multiplexing.
4Device complexity
If a single testing unit is shared between device types, then device complexity is reduced, but idle time may occur during switching
Solution Approach 1:
The patent applies preliminary action by pre-configuring the switching mechanisms and control logic within the testing unit to minimize transition time between device types. The switch control section is designed to anticipate and prepare for device type switches, and the physical layout of switches and connections is optimized to reduce reconfiguration time, thereby minimizing idle time while maintaining a single shared testing unit structure.
Data Source
AI summary
A driver for supplying a test signal to a device under test is shared by a plurality of terminals. In this way, the cost and time required for the test of the device under test can be reduced.A testing apparatus 10 relating to the present invention includes a test signal generating section 130 that generates a test signal to be supplied to a device under test 20, a driver 140 that outputs the test signal, a switch 150 that is disposed on a wire between the driver 140 and a first terminal of the device under test 20, a switch 160 that is disposed on a wire between the driver 140 and a second terminal of the device under test 20, and a connection control section 100 that (i) turns on the switch 150 and turns off the switch 160 when the test signal is supplied to the first terminal of the device under test 20, and (ii) turns off the switch 150 and turns on the switch 160 when the test signal is supplied to the second terminal of the device under test 20.