Multi-Core Debug Transport Switching With a Shared DTM
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Solution Overview
Problem
Conventional RISC-V debug systems require multiple debug transport modules (DTMs) to control multiple processors, leading to increased hardware complexity and gate count, which elevates manufacturing costs and complicates debugging operations.
Innovation Solution
A debug system that includes a single debug transport module (DTM) coupled with a module selector to control multiple debug modules (DMs) through a selection data register, allowing the DTM to switch between paths to access different DMs, thereby reducing the need for multiple DTMs and simplifying debugging operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple debug transport modules (DTMs) are used to control multiple processors, then each processor can be accessed independently, but the hardware complexity and gate count increase
Solution Approach 1:
A single DTM is designed to perform multiple functions by controlling multiple DMs through a module selector. The DTM can be dynamically configured to access different DMs (and thus different processing cores) by writing to the module selector, eliminating the need for dedicated DTMs for each processor while maintaining full debugging capability for all cores
Solution Approach 2:
Multiple debugging functions that would traditionally require separate DTMs are merged into a single shared DTM. The module selector acts as a multiplexer that combines multiple DM access paths through one DTM, reducing the overall number of debugging modules needed in the system
2Productivity
If multiple DTMs are used to access multiple processing cores, then debugging operations can be performed on each core, but the circuit area increases
Solution Approach 1:
The single DTM is designed to serve multiple processing cores by dynamically switching its connection target through the module selector. This multi-functional design allows one DTM to replace what would traditionally require multiple DTMs, significantly reducing the circuit area allocated for debugging infrastructure while maintaining the ability to debug all cores
3Reliability
If multiple DTMs are implemented in the hardware platform, then each processor has dedicated debug access, but manufacturing costs increase
Solution Approach 1:
The debugging infrastructure is merged into a shared resource model where one DTM serves multiple processors. This consolidation reduces the total component count and hardware complexity, making the platform easier and less expensive to manufacture while maintaining reliable debugging access to all processors through dynamic configuration
4Productivity
If multiple DTMs are used for multiple processors, then debug operations can proceed in parallel, but the control logic becomes complicated
Solution Approach 1:
The module selector acts as an intermediary between the single DTM and multiple DMs. It manages the switching and routing of debug signals, handling the complexity of multi-core access control. This intermediary absorbs the control logic complexity, keeping the DTM itself simple while enabling coordinated access to multiple processors
Data Source
AI summary
The present application discloses a debug system. The debug system includes a DTM, a first DM, a second DM, and a module selector. The first DM is coupled to a first processing core, and the second DM is coupled to a second processing core. The module selector is coupled to the DTM, the first DM, and the second DM. When a selection data register of the DTM is written with a first value, the DTM controls the module selector to select a first path coupled between the DTM and the first DM so as to access the first processing core through the first path. When the selection data register is written with a second value, the DTM controls the module selector to select a second path coupled between the DTM and the second DM so as to access the second processing core through the second path.