Shared ECC Circuitry for Flexible Bit Protection in LPDDR Memory
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Solution Overview
Problem
Existing memory devices face challenges in achieving efficient error correction and detection while minimizing die area and latency, particularly in LPDDR memory, due to the need for replicated ECC engines and complex masked-write operations.
Innovation Solution
Implementing a configurable ECC circuitry with shared ECC engines across multiple memory banks, allowing for larger ECC values without increasing die size, and enabling/disabling masked-write functionality as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated ECC circuitry is implemented for each memory bank, then error detection and correction capability is improved, but die area consumption increases
Solution Approach 1:
The patent combines multiple ECC engines into a shared resource that services multiple memory banks. The configurable ECC circuitry includes a first ECC engine that can be shared across first and second memory banks, and a second ECC engine that can be shared across second and third memory banks, reducing the total number of dedicated ECC engines while maintaining error correction coverage.
Solution Approach 2:
The ECC engines are designed with multi-functionality to service multiple memory banks. The first ECC engine can service both first and second memory banks, and the second ECC engine can service both second and third memory banks, allowing a single ECC engine to perform multiple error correction functions across different banks.
2Measurement precision
If higher-order ECC values are implemented, then error detection precision is improved, but device complexity increases
Solution Approach 1:
The ECC circuitry is designed to be configurable and dynamic, allowing the system to select between different ECC engine modes and error correction schemes based on operational requirements. The configurable nature enables the system to adjust the level of error correction precision and complexity adaptively rather than being fixed at maximum complexity.
Solution Approach 2:
The patent implements configurable parameters that allow dynamic adjustment of ECC engine operation modes. The system can change operational parameters such as which ECC engine services which memory banks, and what level of error correction is applied, enabling optimization between precision and complexity based on specific operational contexts.
3Adaptability or versatility
If masked-write functionality is enabled, then data manipulation flexibility is improved, but area usage increases
Solution Approach 1:
The masked-write functionality is integrated into the existing configurable ECC circuitry architecture rather than being implemented as separate dedicated circuitry. The ECC engines and masked-write control share resources and operational pathways, combining multiple functions into a unified circuit block that reduces total die area while maintaining both error correction and data manipulation capabilities.
Data Source
AI summary
Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.