Shared ECC Blocks for Memory Banks
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Solution Overview
Problem
Conventional memory devices require dedicated ECC circuitry for each data bank, which occupies substantial floorplan resources and limits memory density and operational speed due to the need for compliance with latency specifications.
Innovation Solution
Implementing shared ECC blocks that serve multiple data banks, reducing the number and size of ECC blocks and facilitating compliance with latency specifications by using input circuitry, output circuitry, block selection circuitry, latching circuitry, and multiplexing circuitry to enable efficient access and operation across different data banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated ECC circuitry is implemented for each data bank, then data integrity and reliability are improved, but floorplan resources are occupied and memory density is limited
Solution Approach 1:
Multiple data banks share a common ECC circuit block instead of each bank having dedicated ECC circuitry. The shared ECC block includes input circuitry to receive data from multiple banks, output circuitry to provide corrected data, and multiplexing circuitry to selectively connect different banks to the shared ECC resources, thereby reducing total ECC circuit area while maintaining error correction capability for all banks.
Solution Approach 2:
The shared ECC circuit block is designed to serve multiple data banks universally. The circuit includes bank selection circuitry and multiplexing mechanisms that allow the same ECC block to process error correction for any of the connected data banks, making the ECC resources multi-functional rather than dedicated to a single bank.
2Reliability
If dedicated ECC circuitry is implemented for each data bank, then error correction capability is improved, but operational speed is limited due to latency specifications
Solution Approach 1:
By merging ECC resources into a shared block, the patent enables more efficient resource utilization. The shared ECC block can service multiple banks in sequence or parallel depending on the implementation, reducing the overall latency compared to dedicated blocks that must each independently handle their bank's operations.
Solution Approach 2:
The ECC circuit includes latching circuitry that can preliminarily capture and hold data from multiple banks, preparing it for error correction processing. This preliminary action allows the ECC block to efficiently manage data flow from multiple banks without being bottlenecked by sequential access delays.
3Reliability
If dedicated ECC circuitry is implemented for each data bank, then data protection is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple dedicated ECC circuits into a single shared ECC block, thereby reducing the total number of separate circuit components. The shared block includes integrated input circuitry, output circuitry, bank selection circuitry, and multiplexing circuitry that collectively replace what would otherwise be multiple independent ECC blocks, simplifying the overall device architecture.
Solution Approach 2:
The shared ECC block acts as an intermediary between multiple data banks and the rest of the memory system. It includes bank selection circuitry and multiplexing mechanisms that mediate access requests from multiple banks, managing the complexity of serving multiple banks through a unified interface rather than requiring direct connections to multiple separate ECC blocks.
Data Source
AI summary
Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.