Shared Frontline ECC Decoder Pooling for SSD Read Channels
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Solution Overview
Problem
Traditional SSD memory systems dedicate highly capable Error Correction Code (ECC) decoders to each read channel, even if their error correcting capability is not fully employed due to varying error rates across different memory devices and conditions, leading to inefficiency.
Innovation Solution
Implementing a pool of frontline ECC decoders that can be shared among all read channels, with an arbiter allocating frames to the most suitable decoder based on availability and error type, allowing for flexible assignment and reduced resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated frontline ECC decoders are allocated for each read channel, then error correction capability is ensured, but resource utilization efficiency deteriorates
Solution Approach 1:
Multiple dedicated frontline ECC decoders are merged into a single shared pool of decoders that serves all read channels. The controller includes a pool of M frontline ECC decoders that are shared among N read channels, where M < N. This merging allows resources to be consolidated and reused across different channels and time periods, improving overall utilization efficiency while maintaining error correction capability through the shared pool.
Solution Approach 2:
The shared pool of frontline ECC decoders is designed to serve multiple functions and multiple read channels simultaneously. The decoders in the pool can be dynamically allocated to any read channel that needs error correction services, making the ECC decoding resources universal rather than channel-specific. This multi-functionality allows the same decoder resources to handle error correction for different channels at different times.
2Reliability
If dedicated frontline ECC decoders are allocated for each read channel, then error correction reliability is maintained, but device complexity increases
Solution Approach 1:
An arbiter is introduced as an intermediary component that manages the allocation of shared frontline ECC decoders to different read channels. The arbiter receives requests from multiple read channels and intelligently allocates available decoders from the shared pool based on current needs and availability. This intermediary layer simplifies the overall system architecture by centralizing the management logic, rather than requiring each channel to have its own dedicated decoder or complex distributed coordination mechanisms.
3Loss of energy
If shared ECC decoders are used among read channels, then resource efficiency improves, but decoding speed may deteriorate
Solution Approach 1:
The shared pool of frontline ECC decoders is segmented into multiple independent decoder units rather than using a single centralized decoder. This segmentation allows multiple decoders to operate in parallel, simultaneously handling error correction for different read channels. By having M decoder units available in the pool, the system can service multiple channels concurrently, maintaining high decoding speeds while improving resource efficiency through sharing.
Data Source
AI summary
Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.