Shared Signal Path ECC Circuit for High-Speed Semiconductor Data
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Solution Overview
Problem
Semiconductor apparatuses face increased bit error rates due to higher operating speeds, necessitating effective error correction mechanisms to maintain reliability and reduce current consumption.
Innovation Solution
An error correction code circuit that generates parity bits and syndrome information, utilizing a data processing circuit to simultaneously output delayed data for both write and read operations, sharing the same signal path to optimize ECC operations and reduce current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating speed is increased to improve productivity, then processing speed is improved, but bit error rate increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing syndrome tables in memory before error correction is needed. During read operations, the syndrome is retrieved from the pre-stored table rather than calculating it in real-time, enabling fast error detection and correction without compromising reliability at high operating speeds.
Solution Approach 2:
The patent uses copying by creating a syndrome table that replicates the error correction capability in a compressed form. The syndrome table stores pre-computed syndrome values for all possible error patterns, allowing the system to copy and retrieve correction information quickly during operations without performing complex real-time calculations.
2Reliability
If separate signal paths are used for write and read operations to improve reliability, then error correction is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single shared signal path that serves both write and read operations for error correction. The same signal path is used to transmit data and syndrome information in both directions, with the controller managing the timing and direction of signal transmission, thereby reducing device complexity while maintaining reliable error correction functionality.
3Reliability
If real-time syndrome calculation is performed to improve error correction accuracy, then reliability is improved, but current consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing syndrome values in a lookup table during idle or low-power periods. During active read operations, the system simply retrieves the pre-computed syndrome from memory rather than performing energy-intensive real-time calculation, significantly reducing current consumption while maintaining high error correction accuracy.
Solution Approach 2:
The patent uses copying by creating a compressed syndrome table that stores error correction information in a space-efficient format. This copied syndrome data can be quickly retrieved from memory without requiring complex real-time computation, thereby reducing the energy consumption of the error correction process while maintaining accuracy.
Data Source
AI summary
The present technology may include an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data, and a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and to share substantially the same signal path in generating the first delay data and in generating the second delay data.