Shared ECC Parity Across SRAM Banks for Bit-Flip Protection
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Solution Overview
Problem
Semiconductor memory devices face challenges such as increased variability in memory cell I-V characteristics due to process, voltage, and temperature variations, as well as susceptibility to chip-level soft errors from alpha particles and cosmic radiation, which current data protection techniques struggle to address effectively.
Innovation Solution
Implementing localized single-bit error parity within each memory bank and sharing single-error correcting or double-error detecting parity across multiple memory banks, using Hamming codes to detect and correct single-bit errors, and storing error correcting codes in a dedicated shared memory bank to reduce overhead and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction techniques are applied to each memory bank independently, then data protection against soft errors is improved, but the overhead and die area increase significantly
Solution Approach 1:
The patent merges the error correction functionality across multiple memory banks by implementing a shared parity bank that serves multiple banks simultaneously. Instead of each memory bank having its own dedicated error correction code (ECC) circuitry and parity storage, the invention combines these resources into a shared infrastructure where a single parity bank protects multiple data banks, thereby reducing overall overhead and die area while maintaining data protection capability
Solution Approach 2:
The shared parity bank serves multiple memory banks universally, acting as a multi-functional component that provides error correction for any of the protected banks. The parity information stored in the shared bank can be used to correct errors in any individual bank, making the error correction system universal rather than dedicated to a single bank, thus improving resource utilization and reducing redundancy
2Quantity of substance
If process geometries are shrunk to reduce cost per bit, then manufacturing cost is reduced, but susceptibility to chip-level soft errors increases
Solution Approach 1:
The patent segments the memory system into multiple independent banks, each with its own data storage and local parity generation capability. This segmentation allows the system to protect against soft errors in scaled geometries by isolating errors to specific banks while using shared parity resources. The segmented architecture enables targeted error correction without requiring full-system redundancy, making it suitable for cost-effective scaled implementations
Solution Approach 2:
The shared parity bank acts as an intermediary between multiple data banks and the error correction logic. It mediates the error protection function by storing parity information that can be used to detect and correct soft errors in any of the connected banks, providing a buffer layer that protects the scaled memory cells from radiation-induced errors without requiring each cell to have redundant protection
Data Source
AI summary
Systems and methods for efficiently implementing data protection techniques that protect data stored in volatile and non-volatile memory devices from soft errors are described. The error correction overprovisioning for a plurality of memory banks may be reduced by implementing localized single-bit error parity to detect single-bit errors within each memory bank of the plurality of memory banks and then sharing a single-error correcting parity or a single-error correcting and double-error detecting parity (SECDEC) over multiple memory banks or over all of the plurality of memory banks. The single-error correcting code (e.g., a Hamming code) may be generated and shared over the plurality of memory banks such that the single-error correcting code may correct single-bit errors across multiple sets of data stored within the plurality of memory banks that correspond with a particular line or row across all of the plurality of memory banks.