Shared Egress Buffer in Multi-Stage Switch

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Solution Overview

Problem

Conventional network switch designs face challenges in achieving low-latency while maintaining high capacity, as complex architectures often introduce scheduling latency and packet collisions, especially in high-throughput switches.

Innovation Solution

The use of an unscheduled crossbar switching fabric combined with a shared egress buffer in a multi-stage network switch eliminates scheduling latency and reduces packet collisions by allowing packets to access the crossbar as soon as an uplink channel becomes available and using shared buffers to handle multiple simultaneous packet arrivals without acceptance failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional scheduling mechanisms are used in high-capacity switches, then packet forwarding control is improved, but scheduling latency increases

Engineering Contradiction:
Improvepacket forwarding controlVSAvoidscheduling latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and removes the centralized scheduling mechanism from the packet forwarding path. By eliminating the scheduler that previously controlled packet transmission timing, the system eliminates scheduling latency while maintaining packet forwarding through direct crossbar switching based on destination egress ports.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The crossbar switching fabric is empowered to autonomously forward packets without external scheduling control. Each packet independently accesses the crossbar when its uplink channel becomes available, and the system self-regulates packet flow through the shared egress buffer without requiring centralized scheduling decisions.

Inventive Principle:
Principle #25Self-service

2Productivity

If complex switch architectures are used to achieve high capacity, then throughput is improved, but device complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidswitch architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the scheduling function from the switch architecture, removing a major source of complexity. The simplified architecture consists of ingress port subsystems, an unscheduled crossbar switching fabric, and egress port subsystems with shared buffers, eliminating the need for complex scheduling algorithms and control logic.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The shared egress buffer serves multiple functions: it acts as a packet queue, a collision resolution mechanism, and a flow regulation point. This single component replaces what would traditionally require multiple specialized components including schedulers, queues, and collision handling logic, thereby reducing overall architectural complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If multiple packets arrive simultaneously at the same egress port, then high throughput is achieved, but packet collisions increase

Engineering Contradiction:
ImprovethroughputVSAvoidpacket delivery success
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges multiple packet streams destined for the same egress port into a single shared buffer. This consolidation allows packets from different ingress ports to be stored together in the shared egress buffer, eliminating collision points and ensuring that all packets are successfully delivered through coordinated egress transmission.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9100313B1Shared egress buffer in a multi-stage switch
Publication Date: 2015.08.04 CISCO TECHNOLOGY INC
  • US9100313B1 patent drawing
  • US9100313B1 patent drawing
  • US9100313B1 patent drawing

AI summary

A multi-stage network switch comprises a plurality of ingress port subsystems each comprising one or more ingress ports configured to receive packets. The switch also comprises a plurality of unscheduled crossbar switching elements connected to the ingress port subsystems that are configured to receive one or more packets from at least one of the ingress port subsystems. The switch further comprises a plurality of egress port subsystems each comprising a memory and a plurality of egress ports. The memory comprises at least one shared egress buffer configured to receive any packets forwarded by the crossbar switching elements from the ingress port subsystems directed to the egress port subsystem, and the egress ports are configured to transmit the packets received in the shared egress buffer.