Shared-Electrode Planar Capacitors for Logic Interconnect Routing
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Solution Overview
Problem
The integration of capacitors, including ferroelectric or paraelectric materials, on the same plane as interconnects of logic devices is challenging, especially when scaling down, due to difficulties in connecting transistors and routing interconnects.
Innovation Solution
A structure that couples multiple capacitors using a shared plate electrode within the immediate vicinity of the capacitors, allowing for flexible shaping and sizing of the plate electrode based on the number and arrangement of capacitors, and incorporating electrode structures between the plate electrode and metal lines to reduce resistance and prevent shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are integrated on the same plane as interconnects of logic devices, then charge storage capacity is improved, but routing complexity and difficulty of connecting transistors increases
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional vertical stacking, where capacitors are positioned above transistors in the z-dimension. This allows charge storage elements to coexist with logic interconnects on the same chip plane without conflicting routing, as connections are made through vertical vias rather than lateral traces.
Solution Approach 2:
The patent introduces shared plate electrodes as intermediary structures that couple multiple capacitors together. These plate electrodes serve as mediating elements between the capacitor arrays and transistor interconnects, simplifying the routing architecture by providing common connection points that reduce the number of individual interconnect paths required.
2Area of moving object
If spacing between capacitors is scaled down, then device density is improved, but integration of connections between transistors and routing interconnects becomes more difficult
Solution Approach 1:
By moving capacitor connections to the vertical dimension through stacked architectures and via-based interconnects, the patent enables tighter lateral spacing between capacitors without increasing lateral routing complexity. The connection integration is handled in the vertical dimension, decoupling density improvements from manufacturing difficulty.
Solution Approach 2:
The patent merges multiple capacitor connections to shared plate electrodes, reducing the number of individual interconnect structures required. This consolidation approach allows capacitors to be placed closer together while sharing common connection pathways, thereby improving density without proportionally increasing manufacturing complexity.
3Reliability
If electrode structures are added between plate electrode and metal lines, then resistance is reduced and shorting is prevented, but device complexity increases
Solution Approach 1:
The patent introduces intermediate electrode structures and insulation layers as mediating elements between the plate electrodes and metal interconnects. These intermediaries serve dual functions: reducing electrical resistance through optimized material pathways and preventing shorting through dielectric isolation, while the modular nature of these layers keeps manufacturing complexity manageable.
Solution Approach 2:
The patent employs composite material structures combining conductive electrode materials with insulating dielectric layers. This composite approach simultaneously achieves low resistance connections and electrical isolation, with each material layer performing its specialized function, thereby improving reliability without requiring overly complex single-material solutions.
Data Source
AI summary
A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.