Shared-Electrode Dual FET Structure for Gaussian I-V Response
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Solution Overview
Problem
Current transistor structures, such as FDSOI and Z2FET, are limited in their functionality and performance, particularly in low-consumption applications and memory applications, and lack the ability to generate current-voltage features with Gaussian-type forms necessary for advanced functions like machine learning.
Innovation Solution
A microelectronic device with two field-effect transistors sharing a common electrode, allowing for additional control points and functionalities, including a buried dielectric layer and a rear gate, enabling fine control of electrical behavior and generation of Gaussian-type current-voltage features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional FDSOI transistors are used, then the device structure is simple and manufacturing is easier, but the device cannot generate Gaussian-type current-voltage features required for machine learning and memory applications
Solution Approach 1:
The patent combines two field-effect transistors into a single integrated device structure with shared components (common source or drain region, shared gate dielectric layer). This merging approach enables the generation of Gaussian-type current-voltage features and provides new functionalities for machine learning and memory applications while maintaining a compact form factor that mitigates the increase in complexity
Solution Approach 2:
The dual-transistor device is designed to perform multiple functions: it can operate as a conventional transistor, generate Gaussian-type current-voltage features for machine learning applications, and function as a memory storage unit. This multi-functionality directly addresses the adaptability requirement while the integrated design keeps the structural complexity manageable
2Adaptability or versatility
If Z2FET transistors are used for memory applications, then partial gate coverage is achieved, but specific current-voltage features like Gaussian-type forms cannot be generated
Solution Approach 1:
The patent merges two field-effect transistors with complementary gate configurations (one with front gate coverage, one with rear gate coverage) into a single device. This combination enables the generation of Gaussian-type current-voltage features that neither transistor type can achieve alone, while the shared substrate and partial component sharing keep the overall structural complexity controlled
3Adaptability or versatility
If FDSOI transistors are used for low-consumption applications, then current leakage is reduced, but new functionalities for machine learning and memory are not enabled
Solution Approach 1:
The dual-transistor device maintains the low-consumption characteristics of FDSOI technology through its insulated substrate structure while simultaneously enabling new functionalities. The device can perform conventional low-power logic operations and also generate Gaussian-type current-voltage features for machine learning applications and serve as a memory storage unit, achieving multi-functionality without sacrificing energy efficiency
Solution Approach 2:
The patent combines the low-power FDSOI transistor structure with additional transistor elements and control mechanisms to enable new functionalities. By merging conventional FDSOI advantages with enhanced structural features, the device achieves both low consumption and advanced capabilities for machine learning and memory applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device provides enhanced performance and new functionalities, enabling applications in memory and machine learning by generating Gaussian-type current-voltage features and supporting advanced logic operations.
Implementation Method 1
a first gate dielectric between the first gate and the first channel, a second gate dielectric between the second gate and the second channel
Implementation Method 2
a first doped zone, constituting one from among the first drain and the first source, a second doped zone, constituting the other from among the first drain and the first source
Implementation Method 3
a rear gate in contact with a lower face of the dielectric layer
Data Source
AI summary
A microelectronic device includes a first transistor having a first drain and a first source, a first doped zone constituting one from among the first drain and the first source, a second doped zone constituting the other from among the first drain and the first source, a second transistor comprising a second drain and a second source, a third doped zone constituting the second source or the second drain, a fourth doped zone constituting the other from among the second drain and the second source, a dielectric layer having an upper face in contact with the four doped zones and a rear gate in contact with a lower face of the dielectric layer. The second doped zone and the fourth doped zone form a common electrode.