Shared-Enable Multi-Bit Level Shifter for Lower Transistor Count
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Solution Overview
Problem
Existing dual rail SRAM architectures face increased memory access time and leakage noise due to voltage level differences, and known single-bit level shifters require excessive transistors for enable logic, consuming power and area.
Innovation Solution
A multi-bit level shifter design where transistors of the enable function are shared across multiple bits, reducing the number of enable transistors required, and an enable circuit is used to process the enable signal, allowing for fewer transistors in the enable logic, specifically using a configuration where the number of transistors is determined by (nbit*2)+3 for nbit >= 2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional single-bit level shifters are used with separate enable logic for each bit, then each bit can be independently controlled, but the number of transistors increases significantly, consuming more power and area
Solution Approach 1:
The patent merges the enable control logic from multiple single-bit level shifters into a single shared enable circuit. Instead of having separate enable transistors for each bit, the invention uses one enable circuit that receives a single enable signal and distributes it to control multiple level shifter stages, thereby reducing the total transistor count while maintaining independent bit control capability through the level shifter's internal structure
Solution Approach 2:
The enable circuit is designed as a universal component that serves multiple level shifter stages simultaneously. This multi-functional enable circuit can control n-bit level shifting operations with a single enable signal, making it applicable to various bit widths without requiring additional enable logic for each bit, thus reducing overall device complexity
2Ease of operation
If more transistors are used in enable logic for precise control, then control precision improves, but power consumption and area increase
Solution Approach 1:
By combining the enable control function into a single shared circuit that serves multiple level shifter stages, the patent reduces the total number of transistors required for enable logic. This merger maintains control precision through proper signal distribution while significantly reducing power consumption associated with numerous individual enable transistors
3Adaptability or versatility
If voltage level shifting is implemented between power domains, then communication between different voltage domains is enabled, but memory access time increases and leakage noise increases
Solution Approach 1:
The patent segments the level shifting operation into multiple staged transformations rather than a single direct shift. By dividing the voltage transition into intermediate steps through multiple level shifter stages, the circuit achieves cross-domain communication while managing the timing and leakage characteristics through controlled incremental voltage changes
Data Source
AI summary
A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.