Shared Enable Circuit for Multi-Bit Level Shifter
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Solution Overview
Problem
Existing dual rail SRAM architectures face challenges with increased memory access time and leakage/noise issues due to the voltage difference between high and low voltage domains, and typical level shifter circuits require a large number of transistors for enable logic, leading to excess area and power consumption.
Innovation Solution
A multi-bit level shifter design where the transistors of the enable function are shared across multiple bits of logic, reducing the number of enable transistors required and implementing a shared enable circuit to minimize component count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a typical level shifter circuit is used with separate enable logic for each bit, then each bit can be independently controlled, but the number of transistors increases significantly leading to excess area and power consumption
Solution Approach 1:
The patent merges the enable control functionality across multiple bits by using a single shared enable circuit that controls the enable nodes of multiple level shifters simultaneously. This consolidation reduces the total transistor count while preserving the ability to independently control each bit through individual enable signals.
Solution Approach 2:
The shared enable circuit is designed to serve multiple level shifters universally, allowing a single circuit structure to control multiple bits. This multi-functional approach enables the same enable logic to be reused across different bits, reducing redundancy and transistor count.
2Reliability
If more transistors are used in the enable logic to provide better control, then the enable function becomes more robust, but the area and power consumption increase
Solution Approach 1:
By merging the enable control logic into a shared circuit, the patent achieves robust enable functionality without replicating complex logic for each bit. The shared enable circuit provides reliable control across multiple level shifters while occupying less area than individual enable circuits would require.
3Ease of manufacture
If separate enable circuits are implemented for each level shifter, then each circuit can be optimized independently, but the total power consumption increases
Solution Approach 1:
The shared enable circuit merges the power-consuming enable logic into a single structure that serves multiple level shifters. This reduces the total power consumption associated with enable logic while maintaining the flexibility to independently control each bit through separate enable signals.
Data Source
AI summary
A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.