Shared Error Calculation Circuit for Semiconductor Data Reliability
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Solution Overview
Problem
The increasing data transmission speed in semiconductor devices, such as DDR2, DDR3, and DDR4, leads to a higher probability of errors during data transmission, necessitating additional devices and methods for ensuring data reliability, particularly in write and read operations.
Innovation Solution
An electronic system that shares a calculation circuit for generating parity and syndrome error information during both write and read operations, utilizing a controller and semiconductor device with an error calculation circuit to enable efficient error correction by generating error correction signals and correcting errors in transfer data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate error calculation circuit is provided for both write and read operations, then error correction reliability is improved, but device area increases
Solution Approach 1:
The error calculation circuit is designed to perform multiple functions: generating parity for write operations and generating syndrome for read operations. By making the circuit universal and capable of adapting to different operational modes, the patent eliminates the need for separate dedicated circuits for write and read error correction, thereby reducing device area while maintaining error correction reliability.
Solution Approach 2:
The error calculation circuit dynamically switches between different operational modes (write mode for parity generation, read mode for syndrome generation) based on the operational requirements. This dynamic adaptability allows a single circuit to replace multiple static circuits, achieving area reduction without compromising the reliability of error correction in either write or read operations.
2Productivity
If data transmission speed is increased, then productivity is improved, but error probability increases
Solution Approach 1:
The error calculation circuit performs preliminary error detection and correction operations during the data transmission process. By proactively calculating parity during writes and syndrome during reads, the system can identify and correct errors before they propagate, thereby maintaining high data transmission speed while compensating for the increased error probability associated with faster transmission.
Solution Approach 2:
The error calculation circuit provides feedback mechanisms through parity generation in write operations and syndrome calculation in read operations. This feedback allows the system to detect and correct transmission errors, creating a closed-loop error management system that maintains reliability even as data transmission speed increases and error probability rises.
Data Source
AI summary
An electronic system includes a controller configured to output a clock, a command, and an address, and configured to receive and transmit data. The electronic system also includes a semiconductor device including an error calculation circuit. The semiconductor device is configured to generate, by the error calculation circuit, a parity including information on an error included in transfer data generated from the data, in a write operation initiated by the command, and to generate, by the error calculation circuit, a syndrome including information on an error included in transfer data generated from internal data, in a read operation initiated by the command.