Shared Error Correction Circuitry for Memory Devices
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Solution Overview
Problem
The existing memory devices with separate encoding and decoding circuitry for error correction coding require a large area, increasing manufacturing complexity and costs, and device size due to the duplication of error correction coding circuitry.
Innovation Solution
Implementing a shared portion of the decoder circuitry as part of the encoder circuitry, which generates syndromes for both encoding and decoding processes, reducing the need for duplicate circuitry and optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate encoding and decoding circuitry is used for error correction coding, then error correction capability is maintained, but device area and manufacturing complexity increase
Solution Approach 1:
The patent merges the encoding and decoding circuitry into a single shared error correction coding circuit that can perform both encoding and decoding operations. The circuit includes a syndrome generator, encoder, and decoder that share common resources, allowing the same physical circuit to execute encoding during write operations and decoding during read operations, thereby reducing the overall device area while maintaining full error correction capability
Solution Approach 2:
The error correction coding circuit is designed as a universal circuit that can perform multiple functions - both encoding and decoding - depending on the operational mode. The circuit responds to control signals to switch between encoding mode (generating parity bits from data) and decoding mode (detecting and correcting errors in retrieved data), eliminating the need for separate dedicated circuits for each function
2Reliability
If separate encoding and decoding circuitry is used for error correction coding, then error correction functionality is complete, but manufacturing complexity and costs increase
Solution Approach 1:
The patent combines multiple error correction functions into a single integrated circuit block. The shared circuit includes common components such as syndrome generators, XOR trees, and lookup tables that serve both encoding and decoding operations, reducing the total component count and simplifying the manufacturing process while maintaining complete error correction functionality
Solution Approach 2:
The circuit employs universal building blocks that can operate in different modes. For example, the same syndrome generator circuit generates syndromes for both encoding (to create parity) and decoding (to detect errors). The circuit responds to control signals to switch between modes, reducing manufacturing complexity by using identical circuitry for multiple purposes
3Reliability
If separate encoding and decoding circuitry is used for error correction coding, then dedicated functionality is achieved, but device size increases
Solution Approach 1:
The patent merges the encoding and decoding circuits into a single shared physical implementation. The circuit uses common resources including syndrome generators, parity bit generators, and error correction logic that are time-multiplexed between encoding and decoding operations, significantly reducing the device volume required compared to having separate dedicated circuits for each function
Data Source
AI summary
Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector.