Shared ESD Protection Circuit for IC Pads and I2C Voltage Limits

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Solution Overview

Problem

Conventional ESD protection circuits occupy significant chip area, are costly, and limit input/output pad voltage during operation, especially in advanced technologies requiring lower trigger levels and I2C bus connections.

Innovation Solution

A single common voltage limiting element is connected between all input/output and power supply pads, with diodes for positive and negative discharges, and a second voltage limiting element with a resistor for power supply pad discharges, allowing shared discharge paths and reduced voltage limitations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD protection circuits are used, then ESD protection is provided, but chip area is significantly occupied

Engineering Contradiction:

ImproveESD protectionVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple ESD protection functions into a single integrated circuit structure that simultaneously protects multiple pads. The protection circuit includes a plurality of ESD protection devices connected in parallel between different pads, sharing common control signals and reference voltages, thereby reducing the total area compared to individual protection circuits for each pad.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The protection circuit is designed to provide universal ESD protection across multiple pads (data pads, address pads, control pads) using a single circuit architecture. The circuit can detect ESD events on any protected pad and respond appropriately, making the protection mechanism multi-functional rather than dedicated to a single pad.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If ESD protection circuit is added, then ESD robustness is improved, but device complexity increases

Engineering Contradiction:

ImproveESD robustnessVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The protection circuit is segmented into functional modules: ESD detection devices for each pad, common reference voltage generation, control logic, and discharge paths. Each module performs a specific function, making the overall complex circuit manageable and maintainable while providing comprehensive protection.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary elements such as reference voltage nodes and control signals that mediate between the ESD detection events and the discharge mechanisms. These intermediaries simplify the control logic by providing standardized interfaces between detection and response functions.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration achieves improved ESD protection with reduced surface area, maintains operational voltage levels, and supports I2C bus connections by limiting voltage increases to a few tens of millivolts, enhancing chip efficiency and reducing standby current.

Implementation Method 1

When the integrated circuit is not in operation, it may be subjected to an electrostatic discharge which may occur between any two pads among those mentioned above

Methodology Applied

Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

The bipolar protections generally offer better a ESD robustness per surface than the MOSSWI type protections, due to the intrinsic negative resistance of their current-voltage curve induced by the bipolar operation

Methodology Applied

Scientific EffectAvalanche breakdown: Avalanche Breakdown

Implementation Method 3

a first voltage limiting module having a first input terminal which is electrically coupled to each first pad by a first diode mounted so as to be reverse biased during the operation of the integrated circuit

Methodology Applied

Scientific EffectDiode conduction: Diode

Implementation Method 4

Methodology Applied

Scientific EffectBipolar transistor operation:

Data Source

PatentUS12470058B2Protection of an integrated circuit against electrostatic discharges

Publication Date: 2025.11.11 STMICROELECTRONICS INT NV

AI summary

An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.