Shared ESD Protection Circuit for Display Panel Test Area Reduction
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits in display panels occupy a large fan-out area, complicating space utilization and manufacturing processes due to the need for different models for various tests.
Innovation Solution
An array substrate design with a non-display area incorporating a shared electrostatic protection circuit that connects test leads to signal lines and driving chip binding pads, allowing a single electrostatic protection circuit to serve both panel lighting and module lighting tests, reducing the need for separate circuits and minimizing fan-out area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different models of ESD protection circuits are developed for different tests, then the ESD protection capability is improved, but the fan-out area and device complexity increase significantly
Solution Approach 1:
The patent implements a universal ESD protection circuit that can handle both panel lighting tests and module lighting tests through a single circuit model. The circuit uses a standardized binding pad structure with test leads that can be configured for different test types, eliminating the need for multiple specialized ESD protection circuits while maintaining comprehensive protection capability across all test scenarios
Solution Approach 2:
The patent merges the previously separate ESD protection circuits for panel lighting and module lighting into a single integrated circuit. By combining the protection functions and using shared test leads and binding pads, the design reduces the overall fan-out area while ensuring both test types are protected against electrostatic discharge
2Reliability
If different models of ESD protection circuits are developed for different tests, then the ESD protection capability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The universal ESD protection circuit design allows the manufacturing process to use a single standardized circuit model for both panel lighting and module lighting tests. This eliminates the need to fabricate, test, and quality-assure multiple different circuit models, significantly simplifying the manufacturing process while maintaining robust ESD protection
3Area of stationary object
If a single ESD protection circuit is shared for both tests, then the fan-out area is reduced, but the adaptability to different test models decreases
Solution Approach 1:
The patent implements a dynamic configuration system where the single ESD protection circuit can be adaptively configured for different test models through software control and configurable test lead connections. The circuit maintains physical compactness while achieving versatility through programmable test patterns and flexible signal routing that can accommodate both panel lighting and module lighting test requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the manufacturing process by reducing the fan-out area and allowing a single electrostatic protection circuit to handle both tests, enhancing space utilization and protecting the drive chip effectively.
Implementation Method 1
the electrostatic protection circuit is configured to output an electrostatic current generated by the array substrate upon externally inputting a test signal and binding the drive chip
Data Source
AI summary
An array substrate, comprises: a plurality of test leads correspondingly connected to a plurality of signal lines respectively through an electrostatic protection circuit; a plurality of driving chip binding pads, which are correspondingly connected to the plurality of test leads respectively through driving signal leads, and are configured to input a driving signal sent from a driving chip to the plurality of signal lines through the plurality of test leads; and the electrostatic protection circuit, which comprises a first connection terminal electrically connected to the plurality of test leads, and a second connection terminal electrically connected to the plurality of signal lines.