Shared-Feedback Flip-Flop for Lower Transistor Count
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Solution Overview
Problem
Traditional master-slave flip flops require separate latches, increasing the complexity and transistor count in integrated circuits, which affects design, test, and circuit area costs.
Innovation Solution
A flip flop design with shared feedback using delayed complementary clock pairs to mimic the behavior of a master-slave flip flop, reducing the need for separate latches and transistors by utilizing a shared storage latch between clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate master and slave latches are used in a traditional master-slave flip flop, then the flip flop can achieve proper data storage and transmission functionality, but the transistor count and circuit complexity increase
Solution Approach 1:
The patent merges the master and slave latches into a single shared feedback latch structure. The feedback path is shared between what would traditionally be separate master and slave latches, reducing the total transistor count while maintaining the master-slave operational behavior through clock-phase-dependent feedback routing
Solution Approach 2:
The patent segments the feedback path into clock-phase-dependent routes using transmission gates. The shared feedback latch is segmented into different operational modes (master phase and slave phase) controlled by clock signals, allowing a single latch structure to perform the functions of both master and slave latches at different times
2Reliability
If separate master and slave latches are used, then proper data storage functionality is achieved, but the circuit area increases
Solution Approach 1:
The patent combines the storage functionality of both master and slave latches into a single shared feedback latch, significantly reducing the circuit area occupied by latch structures. The shared latch uses transmission gates to route feedback signals differently based on clock phase, eliminating the need for separate physical latch structures
Data Source
AI summary
A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.