Shared-Feedback Latch Circuit for Soft Error Resistance
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Solution Overview
Problem
Existing semiconductor latch circuits face challenges in minimizing area occupation and maintaining response speed while enhancing soft error resistance, as existing methods either increase circuit complexity or fail to prevent stationary errors due to soft errors.
Innovation Solution
A latch circuit design incorporating a feedback circuit with multiple inverter stages that applies positive feedback only when input signals of the same phase are simultaneously input, using a predetermined number of amplification stages to reduce the likelihood of stationary errors and maintain response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dynamic latches are prepared with independent feedback loops to increase soft error resistance, then soft error resistance improves, but circuit area increases and response speed decreases
Solution Approach 1:
The patent merges multiple feedback loops into a single shared feedback path. Instead of preparing separate dynamic latches with independent feedback loops, the invention uses one feedback loop that is shared among multiple latch structures, thereby reducing circuit area while maintaining soft error resistance through the combined feedback mechanism
Solution Approach 2:
The feedback loop is designed to serve multiple functions simultaneously - it provides feedback for multiple latch structures and enables soft error resistance across the entire circuit. The single feedback loop acts as a universal component that benefits multiple latch operations rather than requiring dedicated feedback paths for each latch
2Reliability
If multiple dynamic latches are prepared with independent feedback loops to increase soft error resistance, then soft error resistance improves, but response speed decreases
Solution Approach 1:
By merging multiple feedback operations into a single shared feedback loop, the patent reduces the total number of feedback cycles required. This consolidation allows the circuit to achieve soft error resistance without the cumulative delay that would result from multiple independent feedback loops operating in sequence
3Reliability
If parity checking circuitry is added to detect and prevent soft errors, then soft error resistance improves, but circuit complexity and area increase
Solution Approach 1:
The feedback loop is designed to automatically detect and correct soft errors through its inherent operational mechanism. When a soft error occurs, the feedback loop naturally restores the correct logic state without requiring external parity checking circuitry or additional error detection logic, thereby maintaining simplicity while achieving reliability
Data Source
AI summary
A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.