Shared FIFO Control Logic for Multi-Channel ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As modern telecommunication links grow in speed and capacity, managing a large number of channels requires a substantial number of logic registers for FIFO queues, leading to resource inefficiencies and increased complexity in Integrated Circuits (ICs).
Innovation Solution
Implementing a method where data is buffered for a time difference between reception and transmission cycles, using a single FIFO control logic module to manage all channels, reducing the need for separate logic registers by aligning read and write operations through a delay buffer, and storing FIFO control and status data in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate FIFO control logic registers are used for each channel, then each channel can be managed independently, but the number of logic registers grows linearly with the number of channels, increasing device complexity and resource consumption
Solution Approach 1:
The patent merges the FIFO control logic for multiple channels into a single shared control logic module. This single module cycles through different channels to manage their FIFO queues, eliminating the need for separate control logic registers for each channel. The shared control logic reduces the number of registers from O(N) to O(1) while maintaining the ability to manage multiple channels independently through time-division multiplexing.
Solution Approach 2:
The single FIFO control logic module is designed to perform multiple functions by cycling through different channels. It can manage FIFO operations for any channel in the system, making it a universal controller that replaces the need for dedicated control logic for each channel. This multi-functional approach allows the same control hardware to serve all channels throughout the system's operation.
2Device complexity
If a single FIFO control logic module is shared among all channels, then the number of logic registers is reduced, but read and write operations for different channels may overlap in time, causing conflicts
Solution Approach 1:
The shared FIFO control logic operates in a periodic manner, cycling through different channels in a predetermined sequence. Each channel is served in turn during specific time periods, ensuring that read and write operations for different channels do not overlap. This periodic service approach prevents conflicts while maintaining efficient resource utilization across all channels.
Solution Approach 2:
The control logic includes preliminary timing mechanisms that determine when each channel should be accessed based on the cyclic schedule. By pre-calculating and enforcing the timing sequence, the system prevents overlapping operations before they can occur, ensuring reliable operation of the shared FIFO control logic across multiple channels.
3Productivity
If data is buffered immediately upon arrival, then data processing speed is maintained, but the time difference between reception and transmission cycles cannot be compensated, leading to data loss or buffer overflow
Solution Approach 1:
The system performs preliminary buffering of incoming data before the transmission cycle begins. By anticipating the time difference between reception and transmission, the control logic pre-positions data in the FIFO queue during the reception phase, ensuring data is ready for transmission without causing buffer overflow or data loss. This preliminary action compensates for timing discrepancies while maintaining high processing speed.
Data Source
AI summary
Methods, integrated circuits, and computer programs for managing a communication path carrying multiple channels are presented. Each channel includes a first-in first-out (FIFO) queue. In one method, the time difference between the start of a cycle for receiving data in a particular channel and a start of a cycle for transmitting data in the same particular channel is identified. Further, the method includes an operation for buffering arriving data in the communication path. The arriving data is buffered for an amount of time equal to the identified time difference, and the result is delayed data. FIFO registers are loaded from memory, which includes loading FIFO control and status data for a single FIFO queue, where the single FIFO queue is associated with the current channel of the produced delayed data at any time. Additionally, method includes an operation for processing contemporaneously read and write requests for the single FIFO queue using the loaded FIFO registers.