Shared-Fin Logic Cell Layout for Dense Low-Leakage Arrays
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Solution Overview
Problem
As integrated circuits (ICs) continue to downscale, the increased number of standard cells leads to a larger chip area, necessitating a more compact and efficient cell array for both power and speed.
Innovation Solution
A semiconductor structure is developed with a cell array comprising logic cells, where P-type and N-type transistors share semiconductor fins, with varying numbers of fins for each type to optimize performance and power consumption, utilizing single-fin and dual-fin transistors in the same row to balance speed and low power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of standard cells is increased to enhance functionality, then the chip area increases, but the compactness and integration density deteriorate
Solution Approach 1:
The patent merges P-type and N-type transistors into a shared fin structure where both transistor types utilize the same physical fin, thereby reducing the total chip area required while maintaining the functionality of multiple standard cells
Solution Approach 2:
The patent transitions from planar transistor layouts to vertical FinFET structures, utilizing the third dimension (vertical height) to increase transistor density and reduce the horizontal chip area footprint
2Speed
If multi-fin transistors are used to improve performance and speed, then the switching speed increases, but the power consumption and off-state leakage current increase
Solution Approach 1:
The patent segments the fin structure into shared physical fins that are controlled by separate gates for P-type and N-type transistors, allowing independent control of each transistor type while sharing the physical fin infrastructure to reduce overall leakage
Solution Approach 2:
The patent applies different fin configurations locally - single-fin transistors for low-power applications and dual-fin transistors for high-performance applications within the same cell array, optimizing the balance between speed and power consumption based on specific circuit requirements
3Use of energy by moving object
If single-fin transistors are used to reduce power consumption, then the power efficiency improves, but the switching speed and performance decrease
Solution Approach 1:
The patent dynamically selects between single-fin and dual-fin transistor configurations based on the specific logic cell requirements, allowing the cell array to adapt its performance characteristics to match the functional demands of different standard cells
4Ease of manufacture
If the cell array uses uniform fin configurations for all transistors, then the manufacturing simplicity is maintained, but the optimization of both high performance and low power requirements is limited
Solution Approach 1:
The patent segments the fin configuration into standardized single-fin and dual-fin building blocks that can be systematically combined to create logic cells with different performance characteristics, maintaining manufacturing simplicity through reuse of standard components
Solution Approach 2:
The patent creates universal fin structures that can serve multiple functions - the same fin fabrication process produces fins that can be used for both single-fin low-power transistors and dual-fin high-performance transistors, eliminating the need for separate fin fabrication processes
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.