Shared Floating Gate Nonvolatile Memory Cell Area Reduction
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Solution Overview
Problem
The challenge is to reduce the area occupied by nonvolatile memory circuit sections in semiconductor devices while maintaining or increasing memory capacity, without compromising the main circuit area.
Innovation Solution
The solution involves arranging data read transistors, capacitive elements, and data write/erase elements in a configuration where the read transistor and write/erase element are separated by a capacitive element, with shared floating gate electrodes, allowing for efficient use of semiconductor regions and reduced area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity of the nonvolatile memory circuit section is increased, then the storage capability is improved, but the occupied area increases and brings pressure to the main circuit area
Solution Approach 1:
The patent merges the floating gate electrode structures of adjacent memory cells, allowing a single floating gate electrode to serve multiple cells. This consolidation reduces the total area occupied by floating gate electrodes while maintaining the required memory capacity, directly resolving the contradiction between increasing storage capability and reducing occupied area.
Solution Approach 2:
The shared floating gate electrode structure enables one electrode to perform multiple functions by serving as the floating gate for multiple memory cells simultaneously. This multi-functionality increases the effective memory capacity within the same physical footprint, addressing the area constraint while expanding storage capability.
2Area of stationary object
If the area of the nonvolatile memory circuit section is reduced, then the main circuit area is preserved, but the memory capacity may be compromised
Solution Approach 1:
The patent implements a nested arrangement where multiple memory cells are embedded within a shared floating gate electrode structure. This nesting allows multiple functional units to occupy the same spatial envelope, reducing the overall circuit area while maintaining or increasing the effective memory capacity through efficient space utilization.
Solution Approach 2:
The invention transitions from a planar arrangement to a three-dimensional structure by stacking memory cells vertically around the shared floating gate electrode. This dimensional change allows multiple cells to occupy the same footprint area by utilizing the vertical dimension, thereby reducing the occupied area while increasing memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes the area of the nonvolatile memory circuit section, enabling increased memory capacity without increasing the main circuit area, and enhances the reliability and efficiency of data writing and erasing operations.
Implementation Method 1
a capacitive element and a data write/erase element. In the nonvolatile memory cell, the data read transistor and the data write/erase element are disposed away from each other by the capacitive element disposed therebetween
Implementation Method 2
A first electrode of the capacitive element, a second electrode of the data read transistor and a third electrode of the data write/erase element are constituted of part of a common floating gate electrode extending along the direction in which the data read transistor, the capacitive element and the data write/erase element are arranged
Data Source
AI summary
p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.