Shared Frame Codec Architecture for Multi-Core IC Area Reduction
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Solution Overview
Problem
The increasing amount of video data due to higher display resolutions in electronic devices strains IC chips, necessitating significant circuitry resources and complicates the upgrade to newer compression/decompression technologies, leading to inefficiencies and slowed adoption of improved algorithms.
Innovation Solution
Implementing a shared frame compressor-decompressor that provides services to multiple cores, using a controller to arbitrate access and manage requests through a queueing or priority mechanism, allowing for lossless compression/decompression without duplicative circuitry and simplifying workflow upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple separate frame decompressing units are included at multiple different cores, then each core can independently decompress frames, but the area of the IC chip devoted to handling video data increases significantly
Solution Approach 1:
A single frame decompressor unit is designed to serve multiple cores through time-multiplexed operation. The decompressor can be dynamically allocated to different cores based on demand, allowing one unit to perform the function of multiple dedicated units would provide, thereby reducing overall IC chip area while maintaining decompression capability across multiple processing cores.
Solution Approach 2:
The frame decompressor is implemented as a dynamic, shared resource rather than static dedicated units. The system uses arbitration mechanisms to dynamically assign the decompressor to different cores based on current processing needs, enabling flexible resource utilization that reduces hardware area while preserving productivity.
2Quantity of substance
If video data processing capability is increased to handle higher display resolutions, then the device can process more video data, but the area of the IC chip devoted to handling video data becomes greater
Solution Approach 1:
Video processing functions including compression and decompression are consolidated into shared units that can be dynamically allocated to multiple cores. This allows the system to handle larger quantities of video data for high-resolution displays without proportionally increasing IC chip area, as the same hardware resources are reused across different processing tasks.
Solution Approach 2:
Frame compression and decompression units are merged into shared resources that serve multiple processing cores. By combining these functions into common hardware blocks with dynamic allocation, the system achieves high video data processing capacity for UHD and VR/AR applications while minimizing the total area required on the IC chip.
3Adaptability or versatility
If separate frame decompressing units are provided for each core, then upgrade to newer compression/decompression technologies is simplified, but the device complexity and circuitry resources increase
Solution Approach 1:
A universal frame decompressor design serves multiple cores while maintaining the ability to upgrade compression/decompression technologies. The shared architecture uses standardized interfaces and control mechanisms that allow technology updates to be implemented in a single location rather than replicated across multiple cores, thereby maintaining adaptability while reducing overall system complexity.
Data Source
AI summary
Techniques and apparatuses are described for video frame codec architectures. A frame decompressor decompresses compressed frames to produce decompressed frames. A frame decompressor controller arbitrates shared access to the frame decompressor. Multiple cores of an SoC request to receive a decompressed frame from the frame decompressor via the frame decompressor controller. The frame decompressor controller can implement a request queue and can order the servicing of requests based on priority of the requests or requesting cores. The frame decompressor controller can also establish a time-sharing protocol for access by the multiple cores. In some implementations, a video decoder is logically integrated with the frame decompressor and stores portions of a decompressed frame in a video buffer, and a display controller retrieves the portions for display using a synchronization mechanism. In analogous manners, a frame compressor controller can arbitrate shared access to a frame compressor for the multiple cores.