Shared Analog Front-End Receiver for Multi-Protocol Switching

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Solution Overview

Problem

Existing communications receivers often require new hardware when supporting multiple protocols, leading to inefficiencies and increased costs due to the need for separate transceivers or chips for each protocol.

Innovation Solution

A multi-protocol communications receiver design featuring a shared analog front-end with variable gain amplifiers and a subset of operational analog-to-digital converter circuits, allowing it to adapt to different protocols by configuring operational modes, thereby conserving power and reducing hardware requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a new protocol is added to accommodate different communication standards, then protocol compatibility is improved, but device complexity and hardware requirements increase

Engineering Contradiction:
Improveprotocol compatibilityVSAvoidhardware requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal receiver architecture where a single device can handle multiple communication protocols (10GBASE-T, 1000BASE-T, 100BASE-TX) through a shared analog front-end and configurable digital signal processing units. The receiver uses a protocol identification module to detect the incoming protocol type and dynamically configures the processing pipeline accordingly, eliminating the need for separate dedicated hardware for each protocol standard.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs dynamic configuration of the receiver's processing units based on the detected protocol type. The system activates only the necessary processing modules required for the current protocol, allowing the hardware to adapt its operational state in real-time. This dynamic approach enables a single receiver to efficiently support multiple protocols without maintaining all processing paths simultaneously active.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple ADC circuits are activated to process high-speed signals, then signal processing capability is improved, but power consumption increases

Engineering Contradiction:
Improvesignal processing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements selective activation of ADC circuits based on the protocol being processed. For 10GBASE-T protocols requiring full signal processing capability, all ADC circuits are activated. For lower-speed protocols like 1000BASE-T or 100BASE-TX, only a subset of ADC circuits is activated, reducing power consumption while maintaining sufficient processing capability for the current protocol requirements.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system dynamically changes the operational parameters of the ADC circuits based on the detected protocol type. The protocol identification module determines the required sampling rate and number of active ADCs, then configures the analog front-end and digital processing units accordingly. This parameter adjustment allows the receiver to optimize power consumption while maintaining signal processing capability appropriate for each protocol.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8964907B2Multi-protocol communications receiver with shared analog front-end
Publication Date: 2015.02.24 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8964907B2 patent drawing
  • US8964907B2 patent drawing
  • US8964907B2 patent drawing

AI summary

According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.